134     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in hal_av1d_alloc_res()  local
135     RK_U32 max_cnt = p_hal->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;  in hal_av1d_alloc_res()
137     INP_CHECK(ret, NULL == p_hal);  in hal_av1d_alloc_res()
139     MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(VdpuAv1dRegCtx)));  in hal_av1d_alloc_res()
140     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in hal_av1d_alloc_res()
148     if (!p_hal->fast_mode) {  in hal_av1d_alloc_res()
152 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_base, MPP_ALIGN(sizeof(AV1CDFs)…  in hal_av1d_alloc_res()
153 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_out_base, MPP_ALIGN(sizeof(AV1C…  in hal_av1d_alloc_res()
154     BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_info, AV1_TILE_INFO_SIZE));  in hal_av1d_alloc_res()
155 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->film_grain_mem, MPP_ALIGN(sizeof(AV1Film…  in hal_av1d_alloc_res()
156 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->global_model, MPP_ALIGN(GLOBAL_MODEL_SIZ…  in hal_av1d_alloc_res()
157 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_buf, MPP_ALIGN(32 * MaxTiles, 4096)…  in hal_av1d_alloc_res()
170 static MPP_RET vdpu_av1d_filtermem_alloc(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1…  in vdpu_av1d_filtermem_alloc()  argument
226     if (!mpp_buffer_get(p_hal->buf_group, &ctx->filter_mem, MPP_ALIGN(size, SZ_4K)))  in vdpu_av1d_filtermem_alloc()
234     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in hal_av1d_release_res()  local
235     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in hal_av1d_release_res()
237     RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in hal_av1d_release_res()
251     MPP_FREE(p_hal->reg_ctx);  in hal_av1d_release_res()
264     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_init()  local
265     INP_CHECK(ret, NULL == p_hal);  in vdpu_av1d_init()
270         VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_init()
277     mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, rkv_hor_align);  in vdpu_av1d_init()
278     mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, rkv_ver_align);  in vdpu_av1d_init()
279     mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align);  in vdpu_av1d_init()
425 static void set_ref_cb_base(Av1dHalCtx *p_hal, RK_S32 i, RK_S32 val, HalBufs bufs, RK_U32 offset)  in set_ref_cb_base()  argument
427     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in set_ref_cb_base()
441         mpp_dev_set_reg_offset(p_hal->dev, 101, offset);  in set_ref_cb_base()
444         mpp_dev_set_reg_offset(p_hal->dev, 103, offset);  in set_ref_cb_base()
447         mpp_dev_set_reg_offset(p_hal->dev, 105, offset);  in set_ref_cb_base()
450         mpp_dev_set_reg_offset(p_hal->dev, 107, offset);  in set_ref_cb_base()
453         mpp_dev_set_reg_offset(p_hal->dev, 109, offset);  in set_ref_cb_base()
456         mpp_dev_set_reg_offset(p_hal->dev, 111, offset);  in set_ref_cb_base()
459         mpp_dev_set_reg_offset(p_hal->dev, 113, offset);  in set_ref_cb_base()
488 static void set_ref_dbase(Av1dHalCtx *p_hal, RK_S32 i, RK_S32 val,  HalBufs bufs, RK_U32 offset)  in set_ref_dbase()  argument
490     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in set_ref_dbase()
503         mpp_dev_set_reg_offset(p_hal->dev, 135, offset);  in set_ref_dbase()
506         mpp_dev_set_reg_offset(p_hal->dev, 137, offset);  in set_ref_dbase()
509         mpp_dev_set_reg_offset(p_hal->dev, 139, offset);  in set_ref_dbase()
512         mpp_dev_set_reg_offset(p_hal->dev, 141, offset);  in set_ref_dbase()
515         mpp_dev_set_reg_offset(p_hal->dev, 143, offset);  in set_ref_dbase()
518         mpp_dev_set_reg_offset(p_hal->dev, 145, offset);  in set_ref_dbase()
521         mpp_dev_set_reg_offset(p_hal->dev, 147, offset);  in set_ref_dbase()
735 static void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in set_frame_sign_bias()  argument
738     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in set_frame_sign_bias()
759 static void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_set_prob()  argument
761     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_set_prob()
778 static void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_A…  in vdpu_av1d_set_reference_frames()  argument
809     set_frame_sign_bias(p_hal, dxva);  in vdpu_av1d_set_reference_frames()
843         set_ref_cb_base(p_hal,  ref, idx, ctx->tile_out_bufs, y_stride);  in vdpu_av1d_set_reference_frames()
844         set_ref_dbase  (p_hal,  ref, idx, ctx->tile_out_bufs, mv_offset);  in vdpu_av1d_set_reference_frames()
1058                 mpp_dev_set_reg_offset(p_hal->dev, 81, mv_offset);  in vdpu_av1d_set_reference_frames()
1099 static void vdpu_av1d_superres_params(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_superres_params()  argument
1112     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_superres_params()
1207     mpp_dev_set_reg_offset(p_hal->dev, 89, ctx->filt_info[SR_COL].offset);  in vdpu_av1d_superres_params()
1211 static void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_set_picture_dimensions()  argument
1215     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_picture_dimensions()
1226     vdpu_av1d_superres_params(p_hal, dxva);  in vdpu_av1d_set_picture_dimensions()
1393 static void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_set_loopfilter()  argument
1395     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_loopfilter()
1426     mpp_dev_set_reg_offset(p_hal->dev, 183, ctx->filt_info[DB_CTRL_COL].offset);  in vdpu_av1d_set_loopfilter()
1429 static void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_set_global_model()  argument
1431     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_global_model()
1520 static void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_set_tile_info_mem()  argument
1522     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_set_tile_info_mem()
1526     RK_U32 stream_len =  p_hal->strm_len - tmp;  in vdpu_av1d_set_tile_info_mem()
1610 static void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_set_cdef()  argument
1616     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_cdef()
1639     mpp_dev_set_reg_offset(p_hal->dev, 85, ctx->filt_info[CDEF_COL].offset);  in vdpu_av1d_set_cdef()
1642 static void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)  in vdpu_av1d_set_lr()  argument
1644     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;  in vdpu_av1d_set_lr()
1657     mpp_dev_set_reg_offset(p_hal->dev, 91, ctx->filt_info[LR_COL].offset);  in vdpu_av1d_set_lr()
1820     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_setup_tile_bufs()  local
1821     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_setup_tile_bufs()
1847     ctx->tile_out_count = mpp_buf_slot_get_count(p_hal->slots);  in vdpu_av1d_setup_tile_bufs()
1856     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_gen_regs()  local
1857     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_gen_regs()
1870     INP_CHECK(ret, NULL == p_hal);  in vdpu_av1d_gen_regs()
1881     if (p_hal->fast_mode) {  in vdpu_av1d_gen_regs()
1897     vdpu_av1d_setup_tile_bufs(p_hal, dxva);  in vdpu_av1d_gen_regs()
1902         ret = vdpu_av1d_filtermem_alloc(p_hal, ctx, dxva);  in vdpu_av1d_gen_regs()
1912     mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);  in vdpu_av1d_gen_regs()
1913     mpp_buf_slot_get_prop(p_hal ->slots, task->dec.output, SLOT_BUFFER, &buffer);  in vdpu_av1d_gen_regs()
1914     mpp_buf_slot_get_prop(p_hal ->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);  in vdpu_av1d_gen_regs()
1921     p_hal->strm_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet);  in vdpu_av1d_gen_regs()
1967     vdpu_av1d_set_global_model(p_hal, dxva);  in vdpu_av1d_gen_regs()
1968     vdpu_av1d_set_tile_info_mem(p_hal, dxva);  in vdpu_av1d_gen_regs()
1972         vdpu_av1d_set_reference_frames(p_hal, ctx, dxva);  in vdpu_av1d_gen_regs()
1975     vdpu_av1d_set_loopfilter(p_hal, dxva);  in vdpu_av1d_gen_regs()
1976     vdpu_av1d_set_picture_dimensions(p_hal, dxva);  in vdpu_av1d_gen_regs()
1977     vdpu_av1d_set_cdef(p_hal, dxva);  in vdpu_av1d_gen_regs()
1978     vdpu_av1d_set_lr(p_hal, dxva);  in vdpu_av1d_gen_regs()
1980     vdpu_av1d_set_prob(p_hal, dxva);  in vdpu_av1d_gen_regs()
2014         size = MPP_ALIGN(p_hal->strm_len, 1);  in vdpu_av1d_gen_regs()
2116         mpp_dev_set_reg_offset(p_hal->dev, 99, y_stride);  in vdpu_av1d_gen_regs()
2118         mpp_dev_set_reg_offset(p_hal->dev, 133, mv_offset);  in vdpu_av1d_gen_regs()
2125         regs->swreg258.sw_strm_buffer_len = MPP_ALIGN(p_hal->strm_len, 128);//  in vdpu_av1d_gen_regs()
2127         regs->swreg6.sw_stream_len  = MPP_ALIGN(p_hal->strm_len, 128);//p_hal->strm_len - offset;  in vdpu_av1d_gen_regs()
2131         mpp_dev_set_reg_offset(p_hal->dev, 169, offset);  in vdpu_av1d_gen_regs()
2133         AV1D_DBG(AV1D_DBG_LOG, "stream len %d\n", p_hal->strm_len);  in vdpu_av1d_gen_regs()
2230         mpp_dev_set_reg_offset(p_hal->dev, 328, y_stride);  in vdpu_av1d_gen_regs()
2240     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_start()  local
2241     INP_CHECK(ret, NULL == p_hal);  in vdpu_av1d_start()
2247     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_start()
2248     VdpuAv1dRegSet *regs = p_hal->fast_mode ?  in vdpu_av1d_start()
2251     MppDev dev = p_hal->dev;  in vdpu_av1d_start()
2306     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_wait()  local
2308     INP_CHECK(ret, NULL == p_hal);  in vdpu_av1d_wait()
2309     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;  in vdpu_av1d_wait()
2310     VdpuAv1dRegSet *p_regs = p_hal->fast_mode ?  in vdpu_av1d_wait()
2319     ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);  in vdpu_av1d_wait()
2341     if (p_hal->dec_cb) {  in vdpu_av1d_wait()
2353         mpp_callback(p_hal->dec_cb, &m_ctx);  in vdpu_av1d_wait()
2355     if (p_hal->fast_mode)  in vdpu_av1d_wait()
2366     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_reset()  local
2368     INP_CHECK(ret, NULL == p_hal);  in vdpu_av1d_reset()
2378     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_flush()  local
2380     INP_CHECK(ret, NULL == p_hal);  in vdpu_av1d_flush()
2389     Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;  in vdpu_av1d_control()  local
2391     INP_CHECK(ret, NULL == p_hal);  in vdpu_av1d_control()
2401             mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);  in vdpu_av1d_control()