Lines Matching refs:syn
725 vepu541_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, VepuFmt input_fmt, HalEncTask *task) in vepu541_h265_set_patch_info() argument
727 RK_U32 hor_stride = syn->pp.hor_stride; in vepu541_h265_set_patch_info()
728 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height; in vepu541_h265_set_patch_info()
974 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data; in vepu541_h265_set_rc_regs() local
981 mb_wd64 = (syn->pp.pic_width + 63) / 64; in vepu541_h265_set_rc_regs()
982 mb_h64 = (syn->pp.pic_height + 63) / 64; in vepu541_h265_set_rc_regs()
1132 static void vepu541_h265_set_slice_regs(H265eSyntax_new *syn, H265eV541RegSet *regs) in vepu541_h265_set_slice_regs() argument
1134 …regs->synt_sps.smpl_adpt_ofst_en = syn->pp.sample_adaptive_offset_enabled_flag;//slice->m_sps->… in vepu541_h265_set_slice_regs()
1135 regs->synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets; in vepu541_h265_set_slice_regs()
1136 regs->synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps; in vepu541_h265_set_slice_regs()
1137 regs->synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag; in vepu541_h265_set_slice_regs()
1138 regs->synt_sps.tmpl_mvp_en = syn->pp.sps_temporal_mvp_enabled_flag; in vepu541_h265_set_slice_regs()
1139 regs->synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4; in vepu541_h265_set_slice_regs()
1140 regs->synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag; in vepu541_h265_set_slice_regs()
1142 regs->synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag; in vepu541_h265_set_slice_regs()
1143 regs->synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag; in vepu541_h265_set_slice_regs()
1144 regs->synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits; in vepu541_h265_set_slice_regs()
1145 regs->synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag; in vepu541_h265_set_slice_regs()
1146 regs->synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag; in vepu541_h265_set_slice_regs()
1147 regs->synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26; in vepu541_h265_set_slice_regs()
1148 regs->synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag; in vepu541_h265_set_slice_regs()
1149 regs->synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag; in vepu541_h265_set_slice_regs()
1150 regs->synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag; in vepu541_h265_set_slice_regs()
1151 regs->synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag; in vepu541_h265_set_slice_regs()
1152 regs->synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag; in vepu541_h265_set_slice_regs()
1153 regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag; in vepu541_h265_set_slice_regs()
1154 regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth; in vepu541_h265_set_slice_regs()
1155 regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag; in vepu541_h265_set_slice_regs()
1157 regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg; in vepu541_h265_set_slice_regs()
1158 regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg; in vepu541_h265_set_slice_regs()
1159 regs->synt_sli0.merge_up_flag = syn->sp.merge_up_flag; in vepu541_h265_set_slice_regs()
1160 regs->synt_sli0.merge_left_flag = syn->sp.merge_left_flag; in vepu541_h265_set_slice_regs()
1161 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; in vepu541_h265_set_slice_regs()
1163 regs->synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act; in vepu541_h265_set_slice_regs()
1164 regs->synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act; in vepu541_h265_set_slice_regs()
1166 regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd; in vepu541_h265_set_slice_regs()
1168 regs->synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg; in vepu541_h265_set_slice_regs()
1169 regs->synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg; in vepu541_h265_set_slice_regs()
1170 regs->synt_sli0.sli_tmprl_mvp_en = syn->sp.sli_tmprl_mvp_en; in vepu541_h265_set_slice_regs()
1171 regs->enc_pic.tot_poc_num = syn->sp.tot_poc_num; in vepu541_h265_set_slice_regs()
1173 regs->synt_sli0.pic_out_flg = syn->sp.pic_out_flg; in vepu541_h265_set_slice_regs()
1174 regs->synt_sli0.sli_type = syn->sp.slice_type; in vepu541_h265_set_slice_regs()
1175 regs->synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg; in vepu541_h265_set_slice_regs()
1176 regs->synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg; in vepu541_h265_set_slice_regs()
1177 regs->synt_sli0.sli_pps_id = syn->sp.sli_pps_id; in vepu541_h265_set_slice_regs()
1178 regs->synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic; in vepu541_h265_set_slice_regs()
1181 regs->synt_sli1.sli_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;; in vepu541_h265_set_slice_regs()
1182 regs->synt_sli1.sli_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2; in vepu541_h265_set_slice_regs()
1183 regs->synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli; in vepu541_h265_set_slice_regs()
1184 regs->synt_sli1.sli_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis; in vepu541_h265_set_slice_regs()
1185 regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg; in vepu541_h265_set_slice_regs()
1186 regs->synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ? in vepu541_h265_set_slice_regs()
1187 syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset; in vepu541_h265_set_slice_regs()
1188 regs->synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd; in vepu541_h265_set_slice_regs()
1190 regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx; in vepu541_h265_set_slice_regs()
1191 regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg; in vepu541_h265_set_slice_regs()
1192 regs->synt_sli2_rodr.sli_poc_lsb = syn->sp.sli_poc_lsb; in vepu541_h265_set_slice_regs()
1193 regs->synt_sli2_rodr.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len; in vepu541_h265_set_slice_regs()
1197 static void vepu541_h265_set_ref_regs(H265eSyntax_new *syn, H265eV541RegSet *regs) in vepu541_h265_set_ref_regs() argument
1199 regs->synt_ref_mark0.st_ref_pic_flg = syn->sp.st_ref_pic_flg; in vepu541_h265_set_ref_regs()
1200 regs->synt_ref_mark0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0; in vepu541_h265_set_ref_regs()
1201 regs->synt_ref_mark0.num_lt_pic = syn->sp.num_lt_pic; in vepu541_h265_set_ref_regs()
1203 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; in vepu541_h265_set_ref_regs()
1204 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; in vepu541_h265_set_ref_regs()
1205 regs->synt_ref_mark1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0; in vepu541_h265_set_ref_regs()
1206 regs->synt_ref_mark1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1; in vepu541_h265_set_ref_regs()
1207 regs->synt_ref_mark1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2; in vepu541_h265_set_ref_regs()
1208 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; in vepu541_h265_set_ref_regs()
1209 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; in vepu541_h265_set_ref_regs()
1210 regs->synt_ref_mark1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1; in vepu541_h265_set_ref_regs()
1211 regs->synt_ref_mark1.num_neg_pic = syn->sp.num_neg_pic; in vepu541_h265_set_ref_regs()
1212 regs->synt_ref_mark1.num_pos_pic = syn->sp.num_pos_pic; in vepu541_h265_set_ref_regs()
1214 regs->synt_ref_mark1.used_by_s0_flg = syn->sp.used_by_s0_flg; in vepu541_h265_set_ref_regs()
1215 regs->synt_ref_mark2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10; in vepu541_h265_set_ref_regs()
1216 regs->synt_ref_mark2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11; in vepu541_h265_set_ref_regs()
1217 regs->synt_ref_mark3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12; in vepu541_h265_set_ref_regs()
1218 regs->synt_ref_mark3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13; in vepu541_h265_set_ref_regs()
1220 regs->synt_ref_mark4.poc_lsb_lt1 = syn->sp.poc_lsb_lt1; in vepu541_h265_set_ref_regs()
1221 regs->synt_ref_mark5.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1; in vepu541_h265_set_ref_regs()
1222 regs->synt_ref_mark4.poc_lsb_lt2 = syn->sp.poc_lsb_lt2; in vepu541_h265_set_ref_regs()
1223 regs->synt_ref_mark1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2; in vepu541_h265_set_ref_regs()
1224 regs->synt_ref_mark5.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2; in vepu541_h265_set_ref_regs()
1225 regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0; in vepu541_h265_set_ref_regs()
1226 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; in vepu541_h265_set_ref_regs()
1230 static void vepu541_h265_set_me_regs(H265eV541HalContext *ctx, H265eSyntax_new *syn, H265eV541RegSe… in vepu541_h265_set_me_regs() argument
1236 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu541_h265_set_me_regs()
1245 if (syn->pp.pic_width < merangx + 60 || syn->pp.pic_width <= 352) { in vepu541_h265_set_me_regs()
1246 if (merangx > syn->pp.pic_width ) { in vepu541_h265_set_me_regs()
1247 merangx = syn->pp.pic_width; in vepu541_h265_set_me_regs()
1252 if (syn->pp.pic_height < merangy + 60 || syn->pp.pic_height <= 288) { in vepu541_h265_set_me_regs()
1253 if (merangy > syn->pp.pic_height) { in vepu541_h265_set_me_regs()
1254 merangy = syn->pp.pic_height; in vepu541_h265_set_me_regs()
1285 if (syn->pp.sps_temporal_mvp_enabled_flag && in vepu541_h265_set_me_regs()
1295 if (syn->pp.pic_width > 2688) { in vepu541_h265_set_me_regs()
1297 } else if (syn->pp.pic_width > 2048) { in vepu541_h265_set_me_regs()
1326 static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs, in vepu540_h265_set_me_ram() argument
1331 if (syn->pp.tiles_enabled_flag == 0) { in vepu540_h265_set_me_ram()
1335 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu540_h265_set_me_ram()
1337 RK_S32 tile_ctu_endx = tile_start_x + syn->pp.column_width_minus1[index]; in vepu540_h265_set_me_ram()
1391 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data; in vepu54x_h265_set_hw_address() local
1399 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx); in vepu54x_h265_set_hw_address()
1400 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx); in vepu54x_h265_set_hw_address()
1401 if (!syn->sp.non_reference_flag) { in vepu54x_h265_set_hw_address()
1417 if (syn->pp.tiles_enabled_flag) { in vepu54x_h265_set_hw_address()
1505 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data; in hal_h265e_v541_gen_regs() local
1513 pic_width_align8 = (syn->pp.pic_width + 7) & (~7); in hal_h265e_v541_gen_regs()
1514 pic_height_align8 = (syn->pp.pic_height + 7) & (~7); in hal_h265e_v541_gen_regs()
1515 pic_wd64 = (syn->pp.pic_width + 63) / 64; in hal_h265e_v541_gen_regs()
1516 pic_h64 = (syn->pp.pic_height + 63) / 64; in hal_h265e_v541_gen_regs()
1540 regs->enc_rsl.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v541_gen_regs()
1541 ? (8 - (syn->pp.pic_width & 0x7)) : 0; in hal_h265e_v541_gen_regs()
1543 regs->enc_rsl.pic_hfill = (syn->pp.pic_height & 0x7) in hal_h265e_v541_gen_regs()
1544 ? (8 - (syn->pp.pic_height & 0x7)) : 0; in hal_h265e_v541_gen_regs()
1547 regs->enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered in hal_h265e_v541_gen_regs()
1581 regs->src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0; in hal_h265e_v541_gen_regs()
1584 vepu541_h265_set_patch_info(ctx->dev, syn, (VepuFmt)fmt->format, task); in hal_h265e_v541_gen_regs()
1595 vepu541_h265_set_me_regs(ctx, syn, regs); in hal_h265e_v541_gen_regs()
1601 if (syn->pp.num_long_term_ref_pics_sps) { in hal_h265e_v541_gen_regs()
1610 regs->rdo_cfg.seq_scaling_matrix_present_flg = syn->pp.scaling_list_enabled_flag; in hal_h265e_v541_gen_regs()
1611 regs->synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type); in hal_h265e_v541_gen_regs()
1618 vepu541_h265_set_slice_regs(syn, regs); in hal_h265e_v541_gen_regs()
1620 vepu541_h265_set_ref_regs(syn, regs); in hal_h265e_v541_gen_regs()
1637 void hal_h265e_v540_set_uniform_tile(H265eV541RegSet *regs, H265eSyntax_new *syn, in hal_h265e_v540_set_uniform_tile() argument
1640 if (syn->pp.tiles_enabled_flag) { in hal_h265e_v540_set_uniform_tile()
1641 RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64; in hal_h265e_v540_set_uniform_tile()
1642 RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1; in hal_h265e_v540_set_uniform_tile()
1647 regs->tile_cfg.tile_en = syn->pp.tiles_enabled_flag; in hal_h265e_v540_set_uniform_tile()
1668 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data; in hal_h265e_v540_start() local
1669 RK_U32 title_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1); in hal_h265e_v540_start()
1688 vepu540_h265_set_me_ram(syn, hw_regs, k, tile_start_x); in hal_h265e_v540_start()
1692 vepu541_h265_set_patch_info(ctx->dev, syn, (VepuFmt)fmt->format, enc_task); in hal_h265e_v540_start()
1694 hal_h265e_v540_set_uniform_tile(hw_regs, syn, k, tile_start_x); in hal_h265e_v540_start()
1765 tile_start_x += (syn->pp.column_width_minus1[k] + 1); in hal_h265e_v540_start()