1296         regs->me_ram.cime_rama_h = 12;  in vepu541_h265_set_me_regs()
1298         regs->me_ram.cime_rama_h = 16;  in vepu541_h265_set_me_regs()
1300         regs->me_ram.cime_rama_h = 20;  in vepu541_h265_set_me_regs()
1306         if (regs->me_ram.cime_rama_h / 4 < tmpMin) {  in vepu541_h265_set_me_regs()
1307             tmpMin = regs->me_ram.cime_rama_h / 4;  in vepu541_h265_set_me_regs()
1309         regs->me_ram.cime_rama_max =  in vepu541_h265_set_me_regs()
1312     regs->me_ram.cach_l2_tag      = 0x0;  in vepu541_h265_set_me_regs()
1317         regs->me_ram.cach_l2_tag  = 0x0;  in vepu541_h265_set_me_regs()
1319         regs->me_ram.cach_l2_tag  = 0x1;  in vepu541_h265_set_me_regs()
1321         regs->me_ram.cach_l2_tag  = 0x2;  in vepu541_h265_set_me_regs()
1323         regs->me_ram.cach_l2_tag  = 0x3;  in vepu541_h265_set_me_regs()
1333         regs->me_ram.cime_linebuf_w = pic_cime_temp / 64;  in vepu540_h265_set_me_ram()
1351         regs->me_ram.cime_linebuf_w = pic_cime_temp / 64;  in vepu540_h265_set_me_ram()
1362 …while ((w_temp > ((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4 * 7…  in vepu540_h265_set_me_ram()
1366 …if (w_temp < (RK_S32)((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4…  in vepu540_h265_set_me_ram()
1369         regs->me_ram.cime_rama_h = h_temp;  in vepu540_h265_set_me_ram()
1377         if (regs->me_ram.cime_rama_h / 4 < tmpMin) {  in vepu540_h265_set_me_ram()
1378             tmpMin = regs->me_ram.cime_rama_h / 4;  in vepu540_h265_set_me_ram()
1380 …regs->me_ram.cime_rama_max = (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_sco…  in vepu540_h265_set_me_ram()
1384 …                regs->me_ram.cime_rama_h, regs->me_ram.cime_rama_max, regs->me_ram.cime_linebuf_w);  in vepu540_h265_set_me_ram()