605     ctx->regs           = mpp_calloc(H265eV541RegSet, 1);  in hal_h265e_v541_init()
820 static MPP_RET setup_vepu541_intra_refresh(H265eV541RegSet *regs, H265eV541HalContext *ctx, RK_U32 …  in setup_vepu541_intra_refresh()
918 vepu541_h265_set_roi_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs)  in vepu541_h265_set_roi_regs()
972 static MPP_RET vepu541_h265_set_rc_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask…  in vepu541_h265_set_rc_regs()
1066     H265eV541RegSet *regs = ctx->regs;  in vepu541_h265_set_pp_regs()
1132 static void vepu541_h265_set_slice_regs(H265eSyntax_new *syn, H265eV541RegSet *regs)  in vepu541_h265_set_slice_regs()
1197 static void vepu541_h265_set_ref_regs(H265eSyntax_new *syn, H265eV541RegSet *regs)  in vepu541_h265_set_ref_regs()
1230 …oid vepu541_h265_set_me_regs(H265eV541HalContext *ctx, H265eSyntax_new *syn, H265eV541RegSet *regs)  in vepu541_h265_set_me_regs()
1326 static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs,  in vepu540_h265_set_me_ram()
1386 void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask *task)  in vepu54x_h265_set_hw_address()
1455 static void setup_vepu541_split(H265eV541RegSet *regs, MppEncSliceSplit *cfg)  in setup_vepu541_split()
1506     H265eV541RegSet *regs = ctx->regs;  in hal_h265e_v541_gen_regs()
1522     memset(regs, 0, sizeof(H265eV541RegSet));  in hal_h265e_v541_gen_regs()
1637 void hal_h265e_v540_set_uniform_tile(H265eV541RegSet *regs, H265eSyntax_new *syn,  in hal_h265e_v540_set_uniform_tile()
1684         H265eV541RegSet *hw_regs = ctx->regs;  in hal_h265e_v540_start()
1707         cfg.size = sizeof(H265eV541RegSet);  in hal_h265e_v540_start()
1736         for (i = 0; i < sizeof(H265eV541RegSet) / 4; i++) {  in hal_h265e_v540_start()
1799         cfg.size = sizeof(H265eV541RegSet);  in hal_h265e_v541_start()
1837     for (i = 0; i < sizeof(H265eV541RegSet) / 4; i++) {  in hal_h265e_v541_start()