79     H264eSps                *sps;  member
533             ctx->sps = desc->p;  in update_vepu580_syntax()
606     hw_cfg->hw_log2_max_frame_num_minus4 = ctx->sps->log2_max_frame_num_minus4;  in hal_h264e_vepu580_get_task()
891 static void setup_vepu580_codec(HalVepu580RegSet *regs, H264eSps *sps,  in setup_vepu580_codec()  argument
903     regs->reg_base.synt_sps.max_fnum       = sps->log2_max_frame_num_minus4;  in setup_vepu580_codec()
904     regs->reg_base.synt_sps.drct_8x8       = sps->direct8x8_inference;  in setup_vepu580_codec()
905     regs->reg_base.synt_sps.mpoc_lm4       = sps->log2_max_poc_lsb_minus4;  in setup_vepu580_codec()
1104 static void setup_vepu580_rdo_pred(HalVepu580RegSet *regs, H264eSps *sps,  in setup_vepu580_rdo_pred()  argument
1120     regs->reg_base.rdo_cfg.rect_size    = (sps->profile_idc == H264_PROFILE_BASELINE &&  in setup_vepu580_rdo_pred()
1121                                            sps->level_idc <= H264_LEVEL_3_0) ? 1 : 0;  in setup_vepu580_rdo_pred()
1123     regs->reg_base.rdo_cfg.vlc_lmt      = (sps->profile_idc < H264_PROFILE_MAIN) &&  in setup_vepu580_rdo_pred()
1249     H264eSps *sps = ctx->sps;  in setup_vepu580_rc_base()  local
1251     RK_S32 mb_w = sps->pic_width_in_mbs;  in setup_vepu580_rc_base()
1252     RK_S32 mb_h = sps->pic_height_in_mbs;  in setup_vepu580_rc_base()
1486     RK_U32 mb_w = ctx->sps->pic_width_in_mbs;  in setup_vepu580_intra_refresh()
1487     RK_U32 mb_h = ctx->sps->pic_height_in_mbs;  in setup_vepu580_intra_refresh()
1728 static void calc_cime_parameter(HalVepu580RegSet *regs, H264eSps *sps)  in calc_cime_parameter()  argument
1736     RK_S32 pic_wd64 = MPP_ALIGN(sps->pic_width_in_mbs * 16, 64) / 64;  in calc_cime_parameter()
1813 static void setup_vepu580_me(HalVepu580RegSet *regs, H264eSps *sps,  in setup_vepu580_me()  argument
1816     RK_S32 level_idc = sps->level_idc;  in setup_vepu580_me()
1853     if (cime_blk_w_max / 4 * 2 > (sps->pic_width_in_mbs * 2 + 1) / 2)  in setup_vepu580_me()
1854         cime_blk_w_max = (sps->pic_width_in_mbs * 2 + 1) / 2 / 2 * 4;  in setup_vepu580_me()
1856     if (cime_blk_h_max / 4 > MPP_ALIGN(sps->pic_height_in_mbs * 16, 64) / 128 * 4)  in setup_vepu580_me()
1857         cime_blk_h_max = MPP_ALIGN(sps->pic_height_in_mbs * 16, 64) / 128 * 16;  in setup_vepu580_me()
1872 …regs->reg_base.me_cfg.mv_limit  = (sps->level_idc > 20) ? 2 : ((sps->level_idc >= 11) ? 1 : 0);//2;  in setup_vepu580_me()
1878     calc_cime_parameter(regs, sps);  in setup_vepu580_me()
2119     H264eSps *sps = ctx->sps;  in hal_h264e_vepu580_gen_regs()  local
2139     setup_vepu580_codec(regs, sps, pps, slice);  in hal_h264e_vepu580_gen_regs()
2140     setup_vepu580_rdo_pred(regs, sps, pps, slice);  in hal_h264e_vepu580_gen_regs()
2158     setup_vepu580_me(regs, sps, slice);  in hal_h264e_vepu580_gen_regs()
2461     RK_U32 mb_w = ctx->sps->pic_width_in_mbs;  in hal_h264e_vepu580_ret_task()
2462     RK_U32 mb_h = ctx->sps->pic_height_in_mbs;  in hal_h264e_vepu580_ret_task()