Lines Matching refs:reg_s3
1909 regs->reg_s3.iprd_wgt_qp_hevc_0_51[0] = 0; in setup_vepu580_l2()
1911 regs->reg_s3.iprd_wgt_qp_hevc_0_51[51] = 0; in setup_vepu580_l2()
1914 memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); in setup_vepu580_l2()
1916 memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); in setup_vepu580_l2()
1918 memset(regs->reg_s3.iprd_wgt_qp_hevc_0_51, 0, H264E_LAMBDA_TAB_SIZE); in setup_vepu580_l2()
1923 regs->reg_s3.lvl32_intra_CST_THD0.lvl4_intra_cst_thd0 = 1; in setup_vepu580_l2()
1924 regs->reg_s3.lvl32_intra_CST_THD0.lvl4_intra_cst_thd1 = 4; in setup_vepu580_l2()
1925 regs->reg_s3.lvl32_intra_CST_THD1.lvl4_intra_cst_thd2 = 9; in setup_vepu580_l2()
1926 regs->reg_s3.lvl32_intra_CST_THD1.lvl4_intra_cst_thd3 = 36; in setup_vepu580_l2()
1928 regs->reg_s3.lvl16_intra_CST_THD0.lvl8_intra_chrm_cst_thd0 = 1; in setup_vepu580_l2()
1929 regs->reg_s3.lvl16_intra_CST_THD0.lvl8_intra_chrm_cst_thd1 = 4; in setup_vepu580_l2()
1930 regs->reg_s3.lvl16_intra_CST_THD1.lvl8_intra_chrm_cst_thd2 = 9; in setup_vepu580_l2()
1931 regs->reg_s3.lvl16_intra_CST_THD1.lvl8_intra_chrm_cst_thd3 = 36; in setup_vepu580_l2()
1933 regs->reg_s3.lvl8_intra_CST_THD0.lvl8_intra_cst_thd0 = 1; in setup_vepu580_l2()
1934 regs->reg_s3.lvl8_intra_CST_THD0.lvl8_intra_cst_thd1 = 4; in setup_vepu580_l2()
1935 regs->reg_s3.lvl8_intra_CST_THD1.lvl8_intra_cst_thd2 = 9; in setup_vepu580_l2()
1936 regs->reg_s3.lvl8_intra_CST_THD1.lvl8_intra_cst_thd3 = 36; in setup_vepu580_l2()
1938 regs->reg_s3.lvl16_intra_UL_CST_THD.lvl16_intra_ul_cst_thld = 0; in setup_vepu580_l2()
1939 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt0 = 48; in setup_vepu580_l2()
1940 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt1 = 60; in setup_vepu580_l2()
1941 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt2 = 40; in setup_vepu580_l2()
1942 regs->reg_s3.lvl32_intra_CST_WGT0.lvl8_intra_cst_wgt3 = 48; in setup_vepu580_l2()
1944 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt0 = 48; in setup_vepu580_l2()
1945 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt1 = 60; in setup_vepu580_l2()
1946 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt2 = 40; in setup_vepu580_l2()
1947 regs->reg_s3.lvl32_intra_CST_WGT1.lvl4_intra_cst_wgt3 = 48; in setup_vepu580_l2()
1949 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt0 = 48; in setup_vepu580_l2()
1950 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt1 = 60; in setup_vepu580_l2()
1951 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt2 = 40; in setup_vepu580_l2()
1952 regs->reg_s3.lvl16_intra_CST_WGT0.lvl16_intra_cst_wgt3 = 48; in setup_vepu580_l2()
1954 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt0 = 36; in setup_vepu580_l2()
1955 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt1 = 42; in setup_vepu580_l2()
1956 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt2 = 28; in setup_vepu580_l2()
1957 regs->reg_s3.lvl16_intra_CST_WGT1.lvl8_intra_chrm_cst_wgt3 = 32; in setup_vepu580_l2()
1959 regs->reg_s3.RDO_QUANT.quant_f_bias_P = 171; in setup_vepu580_l2()
1962 regs->reg_s3.RDO_QUANT.quant_f_bias_I = 683; in setup_vepu580_l2()
1963 regs->reg_s3.ATR_THD0.atr_thd0 = 1; in setup_vepu580_l2()
1964 regs->reg_s3.ATR_THD0.atr_thd1 = 4; in setup_vepu580_l2()
1965 regs->reg_s3.ATR_THD1.atr_thd2 = 36; in setup_vepu580_l2()
1967 regs->reg_s3.RDO_QUANT.quant_f_bias_I = 583; in setup_vepu580_l2()
1968 regs->reg_s3.ATR_THD0.atr_thd0 = 4; in setup_vepu580_l2()
1969 regs->reg_s3.ATR_THD0.atr_thd1 = 16; in setup_vepu580_l2()
1970 regs->reg_s3.ATR_THD1.atr_thd2 = 81; in setup_vepu580_l2()
1972 regs->reg_s3.ATR_THD1.atr_thdqp = 45; in setup_vepu580_l2()
1975 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 16; in setup_vepu580_l2()
1976 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 16; in setup_vepu580_l2()
1977 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu580_l2()
1979 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 22; in setup_vepu580_l2()
1980 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 21; in setup_vepu580_l2()
1981 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 20; in setup_vepu580_l2()
1983 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 20; in setup_vepu580_l2()
1984 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 18; in setup_vepu580_l2()
1985 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu580_l2()
1987 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 25; in setup_vepu580_l2()
1988 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 20; in setup_vepu580_l2()
1989 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu580_l2()
1991 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 25; in setup_vepu580_l2()
1992 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 20; in setup_vepu580_l2()
1993 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 18; in setup_vepu580_l2()
1995 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 25; in setup_vepu580_l2()
1996 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 20; in setup_vepu580_l2()
1997 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu580_l2()
2002 regs->reg_s3.cime_sqi_cfg.cime_sad_mod_sel = 0; in setup_vepu580_l2()
2003 regs->reg_s3.cime_sqi_cfg.cime_sad_use_big_block = 1; in setup_vepu580_l2()
2004 regs->reg_s3.cime_sqi_cfg.cime_pmv_set_zero = 1; in setup_vepu580_l2()
2005 regs->reg_s3.cime_sqi_cfg.cime_pmv_num = 3; in setup_vepu580_l2()
2008 regs->reg_s3.cime_sqi_thd.cime_mvd_th0 = 32; in setup_vepu580_l2()
2009 regs->reg_s3.cime_sqi_thd.cime_mvd_th1 = 80; in setup_vepu580_l2()
2010 regs->reg_s3.cime_sqi_thd.cime_mvd_th2 = 128; in setup_vepu580_l2()
2013 regs->reg_s3.cime_sqi_multi0.cime_multi0 = 4; in setup_vepu580_l2()
2014 regs->reg_s3.cime_sqi_multi0.cime_multi1 = 8; in setup_vepu580_l2()
2015 regs->reg_s3.cime_sqi_multi1.cime_multi2 = 24; in setup_vepu580_l2()
2016 regs->reg_s3.cime_sqi_multi1.cime_multi3 = 24; in setup_vepu580_l2()
2022 regs->reg_s3.rime_sqi_thd.cime_sad_th0 = 50; in setup_vepu580_l2()
2023 regs->reg_s3.rime_sqi_thd.rime_mvd_th0 = 3; in setup_vepu580_l2()
2024 regs->reg_s3.rime_sqi_thd.rime_mvd_th1 = 8; in setup_vepu580_l2()
2025 regs->reg_s3.rime_sqi_multi.rime_multi0 = 4; in setup_vepu580_l2()
2026 regs->reg_s3.rime_sqi_multi.rime_multi1 = 32; in setup_vepu580_l2()
2027 regs->reg_s3.rime_sqi_multi.rime_multi2 = 128; in setup_vepu580_l2()
2030 regs->reg_s3.fme_sqi_thd0.cime_sad_pu16_th = 2; in setup_vepu580_l2()
2033 regs->reg_s3.fme_sqi_thd1.move_lambda = 1; in setup_vepu580_l2()
2239 wr_cfg.reg = ®s->reg_s3; in hal_h264e_vepu580_start()
2240 wr_cfg.size = sizeof(regs->reg_s3); in hal_h264e_vepu580_start()