70     MppDevRegOffCfgs        *offsets;  member
255     if (p->offsets) {  in hal_h264e_vepu580_deinit()
256         mpp_dev_multi_offset_deinit(p->offsets);  in hal_h264e_vepu580_deinit()
257         p->offsets = NULL;  in hal_h264e_vepu580_deinit()
398     mpp_dev_multi_offset_init(&p->offsets, 24);  in hal_h264e_vepu580_init()
399     p->osd_cfg.reg_cfg = p->offsets;  in hal_h264e_vepu580_init()
844     mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align);  in vepu580_h264e_save_pass1_patch()
884     mpp_dev_multi_offset_update(ctx->offsets, 161, frame_size);  in vepu580_h264e_use_pass1_patch()
885     mpp_dev_multi_offset_update(ctx->offsets, 162, frame_size);  in vepu580_h264e_use_pass1_patch()
1352 static void setup_vepu580_io_buf(HalVepu580RegSet *regs, MppDevRegOffCfgs *offsets,  in setup_vepu580_io_buf()  argument
1427     mpp_dev_multi_offset_update(offsets, 161, off_in[0]);  in setup_vepu580_io_buf()
1428     mpp_dev_multi_offset_update(offsets, 162, off_in[1]);  in setup_vepu580_io_buf()
1429     mpp_dev_multi_offset_update(offsets, 172, siz_out);  in setup_vepu580_io_buf()
1430     mpp_dev_multi_offset_update(offsets, 175, off_out);  in setup_vepu580_io_buf()
1664     mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size);  in setup_vepu580_recn_refr()
1665     mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size);  in setup_vepu580_recn_refr()
2068     mpp_dev_multi_offset_update(ctx->offsets, 182, offset);  in setup_vepu580_ext_line_buf()
2148     setup_vepu580_io_buf(regs, ctx->offsets, task);  in hal_h264e_vepu580_gen_regs()
2278         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->offsets);  in hal_h264e_vepu580_start()
2527     mpp_dev_multi_offset_reset(ctx->offsets);  in hal_h264e_vepu580_ret_task()