839     regs->reg_base.enc_pic.cur_frm_ref = 1;  in vepu580_h264e_save_pass1_patch()
842     regs->reg_base.enc_pic.rec_fbc_dis = 1;  in vepu580_h264e_save_pass1_patch()
848     regs->reg_base.enc_pic.slen_fifo = 0;  in vepu580_h264e_save_pass1_patch()
896     regs->reg_base.enc_pic.enc_stnd       = 0;  in setup_vepu580_codec()
897     regs->reg_base.enc_pic.cur_frm_ref    = slice->nal_reference_idc > 0;  in setup_vepu580_codec()
898     regs->reg_base.enc_pic.bs_scp         = 1;  in setup_vepu580_codec()
1289         regs->reg_base.enc_pic.pic_qp    = qp_target;  in setup_vepu580_rc_base()
1303     regs->reg_base.enc_pic.pic_qp       = qp_target;  in setup_vepu580_rc_base()
1563     regs->reg_base.enc_pic.roi_en = 1;  in setup_vepu580_intra_refresh()
1590             regs->reg_base.enc_pic.roi_en = 1;  in setup_vepu580_roi()
1686         regs->reg_base.enc_pic.slen_fifo = 0;  in setup_vepu580_split()
1697         regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;  in setup_vepu580_split()
1698         regs->reg_ctl.int_en.slc_done_en = regs->reg_base.enc_pic.slen_fifo;  in setup_vepu580_split()
1713         regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;  in setup_vepu580_split()
1716             (regs->reg_base.enc_pic.slen_fifo && (slice_num > VEPU580_SLICE_FIFO_LEN)))  in setup_vepu580_split()
2153     regs->reg_base.enc_pic.mei_stor = task->md_info ? 1 : 0;  in hal_h264e_vepu580_gen_regs()