Lines Matching refs:reg_s3
1292 memcpy(regs->reg_s3.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); in setup_vepu540c_l2()
1295 regs->reg_s3.RDO_QUANT.quant_f_bias_I = hw->qbias_i; in setup_vepu540c_l2()
1296 regs->reg_s3.RDO_QUANT.quant_f_bias_P = hw->qbias_p; in setup_vepu540c_l2()
1298 regs->reg_s3.RDO_QUANT.quant_f_bias_I = 683; in setup_vepu540c_l2()
1299 regs->reg_s3.RDO_QUANT.quant_f_bias_P = 341; in setup_vepu540c_l2()
1301 regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_0 = 1; in setup_vepu540c_l2()
1302 regs->reg_s3.iprd_tthdy4_0.iprd_tthdy4_1 = 3; in setup_vepu540c_l2()
1303 regs->reg_s3.iprd_tthdy4_1.iprd_tthdy4_2 = 6; in setup_vepu540c_l2()
1304 regs->reg_s3.iprd_tthdy4_1.iprd_tthdy4_3 = 8; in setup_vepu540c_l2()
1305 regs->reg_s3.iprd_tthdc8_0.iprd_tthdc8_0 = 1; in setup_vepu540c_l2()
1306 regs->reg_s3.iprd_tthdc8_0.iprd_tthdc8_1 = 3; in setup_vepu540c_l2()
1307 regs->reg_s3.iprd_tthdc8_1.iprd_tthdc8_2 = 6; in setup_vepu540c_l2()
1308 regs->reg_s3.iprd_tthdc8_1.iprd_tthdc8_3 = 8; in setup_vepu540c_l2()
1309 regs->reg_s3.iprd_tthdy8_0.iprd_tthdy8_0 = 1; in setup_vepu540c_l2()
1310 regs->reg_s3.iprd_tthdy8_0.iprd_tthdy8_1 = 3; in setup_vepu540c_l2()
1311 regs->reg_s3.iprd_tthdy8_1.iprd_tthdy8_2 = 6; in setup_vepu540c_l2()
1312 regs->reg_s3.iprd_tthdy8_1.iprd_tthdy8_3 = 8; in setup_vepu540c_l2()
1313 regs->reg_s3.iprd_tthd_ul.iprd_tthd_ul = 4; in setup_vepu540c_l2()
1314 regs->reg_s3.iprd_wgty8.iprd_wgty8_0 = 22; in setup_vepu540c_l2()
1315 regs->reg_s3.iprd_wgty8.iprd_wgty8_1 = 23; in setup_vepu540c_l2()
1316 regs->reg_s3.iprd_wgty8.iprd_wgty8_2 = 20; in setup_vepu540c_l2()
1317 regs->reg_s3.iprd_wgty8.iprd_wgty8_3 = 22; in setup_vepu540c_l2()
1318 regs->reg_s3.iprd_wgty4.iprd_wgty4_0 = 22; in setup_vepu540c_l2()
1319 regs->reg_s3.iprd_wgty4.iprd_wgty4_1 = 26; in setup_vepu540c_l2()
1320 regs->reg_s3.iprd_wgty4.iprd_wgty4_2 = 20; in setup_vepu540c_l2()
1321 regs->reg_s3.iprd_wgty4.iprd_wgty4_3 = 22; in setup_vepu540c_l2()
1322 regs->reg_s3.iprd_wgty16.iprd_wgty16_0 = 22; in setup_vepu540c_l2()
1323 regs->reg_s3.iprd_wgty16.iprd_wgty16_1 = 26; in setup_vepu540c_l2()
1324 regs->reg_s3.iprd_wgty16.iprd_wgty16_2 = 20; in setup_vepu540c_l2()
1325 regs->reg_s3.iprd_wgty16.iprd_wgty16_3 = 22; in setup_vepu540c_l2()
1326 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_0 = 18; in setup_vepu540c_l2()
1327 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_1 = 21; in setup_vepu540c_l2()
1328 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_2 = 20; in setup_vepu540c_l2()
1329 regs->reg_s3.iprd_wgtc8.iprd_wgtc8_3 = 19; in setup_vepu540c_l2()
1333 regs->reg_s3.ATR_THD0.atr_thd0 = 1; in setup_vepu540c_l2()
1334 regs->reg_s3.ATR_THD0.atr_thd1 = 2; in setup_vepu540c_l2()
1335 regs->reg_s3.ATR_THD1.atr_thd2 = 6; in setup_vepu540c_l2()
1337 regs->reg_s3.ATR_THD0.atr_thd0 = 2; in setup_vepu540c_l2()
1338 regs->reg_s3.ATR_THD0.atr_thd1 = 4; in setup_vepu540c_l2()
1339 regs->reg_s3.ATR_THD1.atr_thd2 = 9; in setup_vepu540c_l2()
1341 regs->reg_s3.ATR_THD1.atr_thdqp = 32; in setup_vepu540c_l2()
1344 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 16; in setup_vepu540c_l2()
1345 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 16; in setup_vepu540c_l2()
1346 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu540c_l2()
1348 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 22; in setup_vepu540c_l2()
1349 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 21; in setup_vepu540c_l2()
1350 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 20; in setup_vepu540c_l2()
1352 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 20; in setup_vepu540c_l2()
1353 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 18; in setup_vepu540c_l2()
1354 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu540c_l2()
1356 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 25; in setup_vepu540c_l2()
1357 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 20; in setup_vepu540c_l2()
1358 regs->reg_s3.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; in setup_vepu540c_l2()
1360 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 25; in setup_vepu540c_l2()
1361 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 20; in setup_vepu540c_l2()
1362 regs->reg_s3.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 18; in setup_vepu540c_l2()
1364 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 25; in setup_vepu540c_l2()
1365 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 20; in setup_vepu540c_l2()
1366 regs->reg_s3.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; in setup_vepu540c_l2()
1371 regs->reg_s3.cime_sqi_cfg.cime_pmv_num = 1; in setup_vepu540c_l2()
1372 regs->reg_s3.cime_sqi_cfg.cime_fuse = 1; in setup_vepu540c_l2()
1373 regs->reg_s3.cime_sqi_cfg.itp_mode = 0; in setup_vepu540c_l2()
1374 regs->reg_s3.cime_sqi_cfg.move_lambda = 0; in setup_vepu540c_l2()
1375 regs->reg_s3.cime_sqi_cfg.rime_lvl_mrg = 0; in setup_vepu540c_l2()
1376 regs->reg_s3.cime_sqi_cfg.rime_prelvl_en = 0; in setup_vepu540c_l2()
1377 regs->reg_s3.cime_sqi_cfg.rime_prersu_en = 0; in setup_vepu540c_l2()
1380 regs->reg_s3.cime_mvd_th.cime_mvd_th0 = 16; in setup_vepu540c_l2()
1381 regs->reg_s3.cime_mvd_th.cime_mvd_th1 = 48; in setup_vepu540c_l2()
1382 regs->reg_s3.cime_mvd_th.cime_mvd_th2 = 80; in setup_vepu540c_l2()
1385 regs->reg_s3.cime_madp_th.cime_madp_th = 16; in setup_vepu540c_l2()
1388 regs->reg_s3.cime_multi.cime_multi0 = 8; in setup_vepu540c_l2()
1389 regs->reg_s3.cime_multi.cime_multi1 = 12; in setup_vepu540c_l2()
1390 regs->reg_s3.cime_multi.cime_multi2 = 16; in setup_vepu540c_l2()
1391 regs->reg_s3.cime_multi.cime_multi3 = 20; in setup_vepu540c_l2()
1397 regs->reg_s3.rime_mvd_th.rime_mvd_th0 = 1; in setup_vepu540c_l2()
1398 regs->reg_s3.rime_mvd_th.rime_mvd_th1 = 2; in setup_vepu540c_l2()
1399 regs->reg_s3.rime_mvd_th.fme_madp_th = 0; in setup_vepu540c_l2()
1402 regs->reg_s3.rime_madp_th.rime_madp_th0 = 8; in setup_vepu540c_l2()
1403 regs->reg_s3.rime_madp_th.rime_madp_th1 = 16; in setup_vepu540c_l2()
1406 regs->reg_s3.rime_multi.rime_multi0 = 4; in setup_vepu540c_l2()
1407 regs->reg_s3.rime_multi.rime_multi1 = 8; in setup_vepu540c_l2()
1408 regs->reg_s3.rime_multi.rime_multi2 = 12; in setup_vepu540c_l2()
1411 regs->reg_s3.cmv_st_th.cmv_th0 = 64; in setup_vepu540c_l2()
1412 regs->reg_s3.cmv_st_th.cmv_th1 = 96; in setup_vepu540c_l2()
1413 regs->reg_s3.cmv_st_th.cmv_th2 = 128; in setup_vepu540c_l2()
1561 wr_cfg.reg = &ctx->regs_set->reg_s3; in hal_h264e_vepu540c_start()
1562 wr_cfg.size = sizeof(ctx->regs_set->reg_s3); in hal_h264e_vepu540c_start()