278     DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)data;  in vp9d_refine_rcb_size()  local
279     RK_U32 num_tiles = pic_param->log2_tile_rows;  in vp9d_refine_rcb_size()
280     RK_U32 bit_depth = pic_param->BitDepthMinus8Luma + 8;  in vp9d_refine_rcb_size()
335     DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)data;  in hal_vp9d_rcb_info_update()  local
336     RK_U32 num_tiles = pic_param->log2_tile_rows;  in hal_vp9d_rcb_info_update()
337     RK_U32 bit_depth = pic_param->BitDepthMinus8Luma + 8;  in hal_vp9d_rcb_info_update()
338     RK_S32 height = vp9_ver_align(pic_param->height);  in hal_vp9d_rcb_info_update()
339     RK_S32 width  = vp9_ver_align(pic_param->width);  in hal_vp9d_rcb_info_update()
347         vp9d_refine_rcb_size(hw_ctx->rcb_info, hw_regs, width, height, pic_param);  in hal_vp9d_rcb_info_update()
384     DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;  in hal_vp9d_vdpu34x_setup_colmv_buf()  local
385     RK_U32 width = pic_param->width;  in hal_vp9d_vdpu34x_setup_colmv_buf()
386     RK_U32 height = pic_param->height;  in hal_vp9d_vdpu34x_setup_colmv_buf()
435     DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;  in hal_vp9d_vdpu34x_gen_regs()  local
436     RK_U32 frame_ctx_id = pic_param->frame_context_idx;  in hal_vp9d_vdpu34x_gen_regs()
459     intraFlag = (!pic_param->frame_type || pic_param->intra_only);  in hal_vp9d_vdpu34x_gen_regs()
474         vp9_hw_regs->vp9d_param.reg103.txfmmode_rfsh_en = (pic_param->txmode == 4) ? 1 : 0;  in hal_vp9d_vdpu34x_gen_regs()
475 …    vp9_hw_regs->vp9d_param.reg103.interp_filter_switch_en = pic_param->interp_filter == 4 ? 1 : 0;  in hal_vp9d_vdpu34x_gen_regs()
482         !pic_param->error_resilient_mode && !pic_param->parallelmode;  in hal_vp9d_vdpu34x_gen_regs()
483     vp9_hw_regs->vp9d_param.reg103.prob_save_en             = pic_param->refresh_frame_context;  in hal_vp9d_vdpu34x_gen_regs()
484     vp9_hw_regs->vp9d_param.reg103.allow_high_precision_mv  = pic_param->allow_high_precision_mv;  in hal_vp9d_vdpu34x_gen_regs()
494         ref_idx = pic_param->frame_refs[0].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
495         ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
502         ref_idx = pic_param->frame_refs[1].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
503         ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
510         ref_idx = pic_param->frame_refs[2].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
511         ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
520         if (pic_param->show_frame && !pic_param->show_existing_frame)  in hal_vp9d_vdpu34x_gen_regs()
535         if ((pic_param->stVP9Segments.enabled && pic_param->stVP9Segments.update_map) ||  in hal_vp9d_vdpu34x_gen_regs()
536             (hw_ctx->ls_info.last_width != pic_param->width) ||  in hal_vp9d_vdpu34x_gen_regs()
537             (hw_ctx->ls_info.last_height != pic_param->height) ||  in hal_vp9d_vdpu34x_gen_regs()
538             intraFlag || pic_param->error_resilient_mode) {  in hal_vp9d_vdpu34x_gen_regs()
550         if (intraFlag || pic_param->error_resilient_mode) {  in hal_vp9d_vdpu34x_gen_regs()
552                 || pic_param->error_resilient_mode  in hal_vp9d_vdpu34x_gen_regs()
553                 || (pic_param->reset_frame_context == 3)) {  in hal_vp9d_vdpu34x_gen_regs()
555             } else if (pic_param->reset_frame_context == 2) {  in hal_vp9d_vdpu34x_gen_regs()
569 …          tmp = (RK_U32 *)mpp_buffer_get_ptr(hw_ctx->prob_loop_base[pic_param->frame_context_idx]);  in hal_vp9d_vdpu34x_gen_regs()
589             hw_ctx->prob_ctx_valid[frame_ctx_id] |= pic_param->refresh_frame_context;  in hal_vp9d_vdpu34x_gen_regs()
595                          intraFlag, pic_param->parallelmode, frame_ctx_id,  in hal_vp9d_vdpu34x_gen_regs()
596                          pic_param->refresh_frame_context, pic_param->error_resilient_mode);  in hal_vp9d_vdpu34x_gen_regs()
597         if (!pic_param->parallelmode)  in hal_vp9d_vdpu34x_gen_regs()
610     vp9_hw_regs->common.reg013.cur_pic_is_idr = !pic_param->frame_type;  in hal_vp9d_vdpu34x_gen_regs()
622     bit_depth = pic_param->BitDepthMinus8Luma + 8;  in hal_vp9d_vdpu34x_gen_regs()
650     if (!pic_param->intra_only && pic_param->frame_type &&  in hal_vp9d_vdpu34x_gen_regs()
651         !pic_param->error_resilient_mode && hw_ctx->ls_info.last_show_frame) {  in hal_vp9d_vdpu34x_gen_regs()
677         ref_idx = pic_param->frame_refs[i].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
678         ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;  in hal_vp9d_vdpu34x_gen_regs()
679         ref_frame_width_y = pic_param->ref_frame_coded_width[ref_idx];  in hal_vp9d_vdpu34x_gen_regs()
680         ref_frame_height_y = pic_param->ref_frame_coded_height[ref_idx];  in hal_vp9d_vdpu34x_gen_regs()
702         if (pic_param->ref_frame_map[ref_idx].Index7Bits < 0x7f) {  in hal_vp9d_vdpu34x_gen_regs()
703 …mpp_buf_slot_get_prop(p_hal ->slots, pic_param->ref_frame_map[ref_idx].Index7Bits, SLOT_BUFFER, &f…  in hal_vp9d_vdpu34x_gen_regs()
706         if (pic_param->ref_frame_map[ref_idx].Index7Bits < 0x7f) {  in hal_vp9d_vdpu34x_gen_regs()
739 …mpp_log("ref buff address is no valid used out as base slot index 0x%x", pic_param->ref_frame_map[…  in hal_vp9d_vdpu34x_gen_regs()
742 …         mv_buf = hal_bufs_get_buf(hw_ctx->cmv_bufs, pic_param->ref_frame_map[ref_idx].Index7Bits);  in hal_vp9d_vdpu34x_gen_regs()
761     vp9_hw_regs->vp9d_param.reg76.tx_mode               = pic_param->txmode;  in hal_vp9d_vdpu34x_gen_regs()
762     vp9_hw_regs->vp9d_param.reg76.frame_reference_mode  = pic_param->refmode;  in hal_vp9d_vdpu34x_gen_regs()
779 …ram.reg75.last_widthheight_eqcur           = (pic_param->width == hw_ctx->ls_info.last_width) && (…  in hal_vp9d_vdpu34x_gen_regs()
780 …vp9_hw_regs->vp9d_param.reg78.lasttile_size                    = stream_len - pic_param->first_par…  in hal_vp9d_vdpu34x_gen_regs()
784         vp9_hw_regs->vp9d_param.reg88.lref_hor_scale = pic_param->mvscale[0][0];  in hal_vp9d_vdpu34x_gen_regs()
785         vp9_hw_regs->vp9d_param.reg89.lref_ver_scale = pic_param->mvscale[0][1];  in hal_vp9d_vdpu34x_gen_regs()
786         vp9_hw_regs->vp9d_param.reg90.gref_hor_scale = pic_param->mvscale[1][0];  in hal_vp9d_vdpu34x_gen_regs()
787         vp9_hw_regs->vp9d_param.reg91.gref_ver_scale = pic_param->mvscale[1][1];  in hal_vp9d_vdpu34x_gen_regs()
788         vp9_hw_regs->vp9d_param.reg92.aref_hor_scale = pic_param->mvscale[2][0];  in hal_vp9d_vdpu34x_gen_regs()
789         vp9_hw_regs->vp9d_param.reg93.aref_ver_scale = pic_param->mvscale[2][1];  in hal_vp9d_vdpu34x_gen_regs()
807     hw_ctx->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta;  in hal_vp9d_vdpu34x_gen_regs()
809         hw_ctx->ls_info.last_ref_deltas[i] = pic_param->ref_deltas[i];  in hal_vp9d_vdpu34x_gen_regs()
813         hw_ctx->ls_info.last_mode_deltas[i] = pic_param->mode_deltas[i];  in hal_vp9d_vdpu34x_gen_regs()
817         hw_ctx->ls_info.feature_data[i][0] = pic_param->stVP9Segments.feature_data[i][0];  in hal_vp9d_vdpu34x_gen_regs()
818         hw_ctx->ls_info.feature_data[i][1] = pic_param->stVP9Segments.feature_data[i][1];  in hal_vp9d_vdpu34x_gen_regs()
819         hw_ctx->ls_info.feature_data[i][2] = pic_param->stVP9Segments.feature_data[i][2];  in hal_vp9d_vdpu34x_gen_regs()
820         hw_ctx->ls_info.feature_data[i][3] = pic_param->stVP9Segments.feature_data[i][3];  in hal_vp9d_vdpu34x_gen_regs()
821         hw_ctx->ls_info.feature_mask[i]  = pic_param->stVP9Segments.feature_mask[i];  in hal_vp9d_vdpu34x_gen_regs()
824         hw_ctx->ls_info.segmentation_enable_flag_last = pic_param->stVP9Segments.enabled;  in hal_vp9d_vdpu34x_gen_regs()
826     hw_ctx->ls_info.last_show_frame = pic_param->show_frame;  in hal_vp9d_vdpu34x_gen_regs()
827     hw_ctx->ls_info.last_width = pic_param->width;  in hal_vp9d_vdpu34x_gen_regs()
828     hw_ctx->ls_info.last_height = pic_param->height;  in hal_vp9d_vdpu34x_gen_regs()
829     hw_ctx->ls_info.last_intra_only = (!pic_param->frame_type || pic_param->intra_only);  in hal_vp9d_vdpu34x_gen_regs()
831                      pic_param->stVP9Segments.enabled, pic_param->show_frame,  in hal_vp9d_vdpu34x_gen_regs()
832                      pic_param->width, pic_param->height,  in hal_vp9d_vdpu34x_gen_regs()
835     hal_vp9d_rcb_info_update(hal, vp9_hw_regs, pic_param);  in hal_vp9d_vdpu34x_gen_regs()
845     if (pic_param->refresh_frame_context && !pic_param->parallelmode) {  in hal_vp9d_vdpu34x_gen_regs()
1012         DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;  in hal_vp9d_vdpu34x_wait()  local
1016         mpp_callback(p_hal->dec_cb, &pic_param->counts);  in hal_vp9d_vdpu34x_wait()