Lines Matching refs:hw_ctx
88 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_alloc_res() local
89 hw_ctx->offset_count = VDPU34X_OFFSET_COUNT; in hal_vp9d_alloc_res()
90 hw_ctx->offset_segid_cur = 0; in hal_vp9d_alloc_res()
91 hw_ctx->offset_segid_last = MAX_SEGMAP_SIZE_ALIGN_TO_4K; in hal_vp9d_alloc_res()
94 ret = mpp_buffer_get(p_hal->group, &hw_ctx->prob_loop_base[i], PROB_SIZE); in hal_vp9d_alloc_res()
100 ret = mpp_buffer_get(p_hal->group, &hw_ctx->prob_default_base, PROB_SIZE); in hal_vp9d_alloc_res()
108 hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xVp9dRegSet)); in hal_vp9d_alloc_res()
109 … ret = mpp_buffer_get(p_hal->group, &hw_ctx->g_buf[i].probe_base, VDPU34X_PROBE_BUFFER_SIZE); in hal_vp9d_alloc_res()
116 hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xVp9dRegSet)); in hal_vp9d_alloc_res()
117 ret = mpp_buffer_get(p_hal->group, &hw_ctx->probe_base, VDPU34X_PROBE_BUFFER_SIZE); in hal_vp9d_alloc_res()
123 ret = mpp_buffer_get(p_hal->group, &hw_ctx->seg_base, MAX_SEGMAP_SIZE_ALIGN_TO_4K * 2); in hal_vp9d_alloc_res()
136 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_release_res() local
138 if (hw_ctx->prob_default_base) { in hal_vp9d_release_res()
139 ret = mpp_buffer_put(hw_ctx->prob_default_base); in hal_vp9d_release_res()
146 if (hw_ctx->prob_loop_base[i]) { in hal_vp9d_release_res()
147 ret = mpp_buffer_put(hw_ctx->prob_loop_base[i]); in hal_vp9d_release_res()
156 if (hw_ctx->g_buf[i].probe_base) { in hal_vp9d_release_res()
157 ret = mpp_buffer_put(hw_ctx->g_buf[i].probe_base); in hal_vp9d_release_res()
163 if (hw_ctx->g_buf[i].hw_regs) { in hal_vp9d_release_res()
164 mpp_free(hw_ctx->g_buf[i].hw_regs); in hal_vp9d_release_res()
165 hw_ctx->g_buf[i].hw_regs = NULL; in hal_vp9d_release_res()
167 if (hw_ctx->g_buf[i].rcb_buf) { in hal_vp9d_release_res()
168 ret = mpp_buffer_put(hw_ctx->g_buf[i].rcb_buf); in hal_vp9d_release_res()
176 if (hw_ctx->probe_base) { in hal_vp9d_release_res()
177 ret = mpp_buffer_put(hw_ctx->probe_base); in hal_vp9d_release_res()
184 if (hw_ctx->hw_regs) { in hal_vp9d_release_res()
185 mpp_free(hw_ctx->hw_regs); in hal_vp9d_release_res()
186 hw_ctx->hw_regs = NULL; in hal_vp9d_release_res()
188 if (hw_ctx->rcb_buf) { in hal_vp9d_release_res()
189 ret = mpp_buffer_put(hw_ctx->rcb_buf); in hal_vp9d_release_res()
197 if (hw_ctx->cmv_bufs) { in hal_vp9d_release_res()
198 ret = hal_bufs_deinit(hw_ctx->cmv_bufs); in hal_vp9d_release_res()
205 if (hw_ctx->seg_base) { in hal_vp9d_release_res()
206 ret = mpp_buffer_put(hw_ctx->seg_base); in hal_vp9d_release_res()
230 MPP_FREE(p_hal->hw_ctx); in hal_vp9d_vdpu34x_deinit()
238 MEM_CHECK(ret, p_hal->hw_ctx = mpp_calloc_size(void, sizeof(Vdpu34xVp9dCtx))); in hal_vp9d_vdpu34x_init()
239 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_vdpu34x_init() local
241 hw_ctx->mv_base_addr = -1; in hal_vp9d_vdpu34x_init()
242 hw_ctx->pre_mv_base_addr = -1; in hal_vp9d_vdpu34x_init()
260 hw_ctx->last_segid_flag = 1; in hal_vp9d_vdpu34x_init()
334 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_rcb_info_update() local
341 if (hw_ctx->num_row_tiles != num_tiles || in hal_vp9d_rcb_info_update()
342 hw_ctx->bit_depth != bit_depth || in hal_vp9d_rcb_info_update()
343 hw_ctx->width != width || in hal_vp9d_rcb_info_update()
344 hw_ctx->height != height) { in hal_vp9d_rcb_info_update()
346 hw_ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size(hw_ctx->rcb_info, width, height); in hal_vp9d_rcb_info_update()
347 vp9d_refine_rcb_size(hw_ctx->rcb_info, hw_regs, width, height, pic_param); in hal_vp9d_rcb_info_update()
352 for (i = 0; i < MPP_ARRAY_ELEMS(hw_ctx->g_buf); i++) { in hal_vp9d_rcb_info_update()
353 MppBuffer rcb_buf = hw_ctx->g_buf[i].rcb_buf; in hal_vp9d_rcb_info_update()
357 hw_ctx->g_buf[i].rcb_buf = NULL; in hal_vp9d_rcb_info_update()
359 mpp_buffer_get(p_hal->group, &rcb_buf, hw_ctx->rcb_buf_size); in hal_vp9d_rcb_info_update()
360 hw_ctx->g_buf[i].rcb_buf = rcb_buf; in hal_vp9d_rcb_info_update()
363 MppBuffer rcb_buf = hw_ctx->rcb_buf; in hal_vp9d_rcb_info_update()
369 mpp_buffer_get(p_hal->group, &rcb_buf, hw_ctx->rcb_buf_size); in hal_vp9d_rcb_info_update()
370 hw_ctx->rcb_buf = rcb_buf; in hal_vp9d_rcb_info_update()
373 hw_ctx->num_row_tiles = num_tiles; in hal_vp9d_rcb_info_update()
374 hw_ctx->bit_depth = bit_depth; in hal_vp9d_rcb_info_update()
375 hw_ctx->width = width; in hal_vp9d_rcb_info_update()
376 hw_ctx->height = height; in hal_vp9d_rcb_info_update()
383 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_vdpu34x_setup_colmv_buf() local
391 if (hw_ctx->cmv_bufs == NULL || hw_ctx->mv_size < mv_size) { in hal_vp9d_vdpu34x_setup_colmv_buf()
394 if (hw_ctx->cmv_bufs) { in hal_vp9d_vdpu34x_setup_colmv_buf()
395 hal_bufs_deinit(hw_ctx->cmv_bufs); in hal_vp9d_vdpu34x_setup_colmv_buf()
396 hw_ctx->cmv_bufs = NULL; in hal_vp9d_vdpu34x_setup_colmv_buf()
399 hal_bufs_init(&hw_ctx->cmv_bufs); in hal_vp9d_vdpu34x_setup_colmv_buf()
400 if (hw_ctx->cmv_bufs == NULL) { in hal_vp9d_vdpu34x_setup_colmv_buf()
404 hw_ctx->mv_size = mv_size; in hal_vp9d_vdpu34x_setup_colmv_buf()
405 hw_ctx->mv_count = mpp_buf_slot_get_count(p_hal ->slots); in hal_vp9d_vdpu34x_setup_colmv_buf()
406 hal_bufs_setup(hw_ctx->cmv_bufs, hw_ctx->mv_count, 1, &size); in hal_vp9d_vdpu34x_setup_colmv_buf()
434 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_vdpu34x_gen_regs() local
440 if (!hw_ctx->g_buf[i].use_flag) { in hal_vp9d_vdpu34x_gen_regs()
442 hw_ctx->probe_base = hw_ctx->g_buf[i].probe_base; in hal_vp9d_vdpu34x_gen_regs()
444 hw_ctx->hw_regs = hw_ctx->g_buf[i].hw_regs; in hal_vp9d_vdpu34x_gen_regs()
445 hw_ctx->g_buf[i].use_flag = 1; in hal_vp9d_vdpu34x_gen_regs()
458 Vdpu34xVp9dRegSet *vp9_hw_regs = (Vdpu34xVp9dRegSet*)hw_ctx->hw_regs; in hal_vp9d_vdpu34x_gen_regs()
461 memset(hw_ctx->hw_regs, 0, sizeof(Vdpu34xVp9dRegSet)); in hal_vp9d_vdpu34x_gen_regs()
463 hal_vp9d_prob_flag_delta(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data); in hal_vp9d_vdpu34x_gen_regs()
464 mpp_buffer_sync_end(hw_ctx->probe_base); in hal_vp9d_vdpu34x_gen_regs()
466 hal_vp9d_prob_default(mpp_buffer_get_ptr(hw_ctx->prob_default_base), task->dec.syntax.data); in hal_vp9d_vdpu34x_gen_regs()
467 mpp_buffer_sync_end(hw_ctx->prob_default_base); in hal_vp9d_vdpu34x_gen_regs()
485 vp9_hw_regs->vp9d_param.reg103.last_key_frame_flag = hw_ctx->ls_info.last_intra_only; in hal_vp9d_vdpu34x_gen_regs()
519 hw_ctx->col_ref_poc ? hw_ctx->col_ref_poc : vp9_hw_regs->vp9d_param.reg65.cur_poc; in hal_vp9d_vdpu34x_gen_regs()
521 hw_ctx->col_ref_poc = vp9_hw_regs->vp9d_param.reg65.cur_poc; in hal_vp9d_vdpu34x_gen_regs()
523 vp9_hw_regs->vp9d_param.reg100.segid_ref_poc = hw_ctx->segid_ref_poc; in hal_vp9d_vdpu34x_gen_regs()
525 vp9_hw_regs->vp9d_addr.reg169_segidcur_base = mpp_buffer_get_fd(hw_ctx->seg_base); in hal_vp9d_vdpu34x_gen_regs()
526 vp9_hw_regs->vp9d_addr.reg168_segidlast_base = mpp_buffer_get_fd(hw_ctx->seg_base); in hal_vp9d_vdpu34x_gen_regs()
527 if (hw_ctx->last_segid_flag) { in hal_vp9d_vdpu34x_gen_regs()
528 mpp_dev_set_reg_offset(p_hal->dev, 168, hw_ctx->offset_segid_last); in hal_vp9d_vdpu34x_gen_regs()
529 mpp_dev_set_reg_offset(p_hal->dev, 169, hw_ctx->offset_segid_cur); in hal_vp9d_vdpu34x_gen_regs()
531 mpp_dev_set_reg_offset(p_hal->dev, 168, hw_ctx->offset_segid_cur); in hal_vp9d_vdpu34x_gen_regs()
532 mpp_dev_set_reg_offset(p_hal->dev, 169, hw_ctx->offset_segid_last); in hal_vp9d_vdpu34x_gen_regs()
536 (hw_ctx->ls_info.last_width != pic_param->width) || in hal_vp9d_vdpu34x_gen_regs()
537 (hw_ctx->ls_info.last_height != pic_param->height) || in hal_vp9d_vdpu34x_gen_regs()
539 hw_ctx->segid_ref_poc = vp9_hw_regs->vp9d_param.reg65.cur_poc; in hal_vp9d_vdpu34x_gen_regs()
540 hw_ctx->last_segid_flag = !hw_ctx->last_segid_flag; in hal_vp9d_vdpu34x_gen_regs()
554 memset(hw_ctx->prob_ctx_valid, 0, sizeof(hw_ctx->prob_ctx_valid)); in hal_vp9d_vdpu34x_gen_regs()
556 hw_ctx->prob_ctx_valid[frame_ctx_id] = 0; in hal_vp9d_vdpu34x_gen_regs()
568 if (hw_ctx->prob_ctx_valid[frame_ctx_id]) { in hal_vp9d_vdpu34x_gen_regs()
569 … tmp = (RK_U32 *)mpp_buffer_get_ptr(hw_ctx->prob_loop_base[pic_param->frame_context_idx]); in hal_vp9d_vdpu34x_gen_regs()
571 tmp = (RK_U32 *)mpp_buffer_get_ptr(hw_ctx->prob_default_base); in hal_vp9d_vdpu34x_gen_regs()
582 if (hw_ctx->prob_ctx_valid[frame_ctx_id]) { in hal_vp9d_vdpu34x_gen_regs()
584 mpp_buffer_get_fd(hw_ctx->prob_loop_base[frame_ctx_id]); in hal_vp9d_vdpu34x_gen_regs()
586 vp9_hw_regs->vp9d_param.reg99.prob_ref_poc = hw_ctx->prob_ref_poc[frame_ctx_id]; in hal_vp9d_vdpu34x_gen_regs()
588 … vp9_hw_regs->vp9d_addr.reg162_last_prob_base = mpp_buffer_get_fd(hw_ctx->prob_default_base); in hal_vp9d_vdpu34x_gen_regs()
589 hw_ctx->prob_ctx_valid[frame_ctx_id] |= pic_param->refresh_frame_context; in hal_vp9d_vdpu34x_gen_regs()
592 hw_ctx->prob_ref_poc[frame_ctx_id] = vp9_hw_regs->vp9d_param.reg65.cur_poc; in hal_vp9d_vdpu34x_gen_regs()
598 hw_ctx->prob_ref_poc[frame_ctx_id] = vp9_hw_regs->vp9d_param.reg65.cur_poc; in hal_vp9d_vdpu34x_gen_regs()
600 mpp_buffer_get_fd(hw_ctx->prob_loop_base[frame_ctx_id]); in hal_vp9d_vdpu34x_gen_regs()
604 vp9_hw_regs->vp9d_addr.reg160_delta_prob_base = mpp_buffer_get_fd(hw_ctx->probe_base); in hal_vp9d_vdpu34x_gen_regs()
606 hal_vp9d_output_probe(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data); in hal_vp9d_vdpu34x_gen_regs()
607 mpp_buffer_sync_end(hw_ctx->probe_base); in hal_vp9d_vdpu34x_gen_regs()
651 !pic_param->error_resilient_mode && hw_ctx->ls_info.last_show_frame) { in hal_vp9d_vdpu34x_gen_regs()
652 hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr; in hal_vp9d_vdpu34x_gen_regs()
660 vp9_hw_regs->vp9d_addr.reg167_count_prob_base = mpp_buffer_get_fd(hw_ctx->probe_base); in hal_vp9d_vdpu34x_gen_regs()
661 mpp_dev_set_reg_offset(p_hal->dev, 167, hw_ctx->offset_count); in hal_vp9d_vdpu34x_gen_regs()
664 mv_buf = hal_bufs_get_buf(hw_ctx->cmv_bufs, task->dec.output); in hal_vp9d_vdpu34x_gen_regs()
666 hw_ctx->mv_base_addr = vp9_hw_regs->common_addr.reg131_colmv_cur_base; in hal_vp9d_vdpu34x_gen_regs()
667 if (hw_ctx->pre_mv_base_addr < 0) { in hal_vp9d_vdpu34x_gen_regs()
668 hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr; in hal_vp9d_vdpu34x_gen_regs()
670 vp9_hw_regs->vp9d_addr.reg170_ref_colmv_base = hw_ctx->pre_mv_base_addr; in hal_vp9d_vdpu34x_gen_regs()
742 … mv_buf = hal_bufs_get_buf(hw_ctx->cmv_bufs, pic_param->ref_frame_map[ref_idx].Index7Bits); in hal_vp9d_vdpu34x_gen_regs()
751 …vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_qp_delta_en = (hw_ctx->ls_info.feature_mas… in hal_vp9d_vdpu34x_gen_regs()
752 …vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_qp_delta = hw_ctx->ls_info.feature_data… in hal_vp9d_vdpu34x_gen_regs()
753 …vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_loopfitler_value_en = (hw_ctx->ls_info.feature_mas… in hal_vp9d_vdpu34x_gen_regs()
754 …vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_loopfilter_value = hw_ctx->ls_info.feature_data… in hal_vp9d_vdpu34x_gen_regs()
755 …vp9_hw_regs->vp9d_param.reg67_74[i].segid_referinfo_en = (hw_ctx->ls_info.feature_mas… in hal_vp9d_vdpu34x_gen_regs()
756 …vp9_hw_regs->vp9d_param.reg67_74[i].segid_referinfo = hw_ctx->ls_info.feature_data… in hal_vp9d_vdpu34x_gen_regs()
757 …vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_skip_en = (hw_ctx->ls_info.feature_mas… in hal_vp9d_vdpu34x_gen_regs()
760 vp9_hw_regs->vp9d_param.reg67_74[0].segid_abs_delta = hw_ctx->ls_info.abs_delta_last; in hal_vp9d_vdpu34x_gen_regs()
767 …vp9_hw_regs->vp9d_param.reg94.ref_deltas_lastframe |= (hw_ctx->ls_info.last_ref_deltas[i] & 0x7f… in hal_vp9d_vdpu34x_gen_regs()
770 …vp9_hw_regs->vp9d_param.reg75.mode_deltas_lastframe |= (hw_ctx->ls_info.last_mode_deltas[i] & 0x7… in hal_vp9d_vdpu34x_gen_regs()
772 hw_ctx->ls_info.segmentation_enable_flag_last = 0; in hal_vp9d_vdpu34x_gen_regs()
773 hw_ctx->ls_info.last_intra_only = 1; in hal_vp9d_vdpu34x_gen_regs()
776 …vp9_hw_regs->vp9d_param.reg75.segmentation_enable_lstframe = hw_ctx->ls_info.segmentation_enab… in hal_vp9d_vdpu34x_gen_regs()
777 … vp9_hw_regs->vp9d_param.reg75.last_show_frame = hw_ctx->ls_info.last_show_frame; in hal_vp9d_vdpu34x_gen_regs()
778 … vp9_hw_regs->vp9d_param.reg75.last_intra_only = hw_ctx->ls_info.last_intra_only; in hal_vp9d_vdpu34x_gen_regs()
779 …hheight_eqcur = (pic_param->width == hw_ctx->ls_info.last_width) && (pic_param->height =… in hal_vp9d_vdpu34x_gen_regs()
807 hw_ctx->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta; in hal_vp9d_vdpu34x_gen_regs()
809 hw_ctx->ls_info.last_ref_deltas[i] = pic_param->ref_deltas[i]; in hal_vp9d_vdpu34x_gen_regs()
813 hw_ctx->ls_info.last_mode_deltas[i] = pic_param->mode_deltas[i]; in hal_vp9d_vdpu34x_gen_regs()
817 hw_ctx->ls_info.feature_data[i][0] = pic_param->stVP9Segments.feature_data[i][0]; in hal_vp9d_vdpu34x_gen_regs()
818 hw_ctx->ls_info.feature_data[i][1] = pic_param->stVP9Segments.feature_data[i][1]; in hal_vp9d_vdpu34x_gen_regs()
819 hw_ctx->ls_info.feature_data[i][2] = pic_param->stVP9Segments.feature_data[i][2]; in hal_vp9d_vdpu34x_gen_regs()
820 hw_ctx->ls_info.feature_data[i][3] = pic_param->stVP9Segments.feature_data[i][3]; in hal_vp9d_vdpu34x_gen_regs()
821 hw_ctx->ls_info.feature_mask[i] = pic_param->stVP9Segments.feature_mask[i]; in hal_vp9d_vdpu34x_gen_regs()
823 if (!hw_ctx->ls_info.segmentation_enable_flag_last) in hal_vp9d_vdpu34x_gen_regs()
824 hw_ctx->ls_info.segmentation_enable_flag_last = pic_param->stVP9Segments.enabled; in hal_vp9d_vdpu34x_gen_regs()
826 hw_ctx->ls_info.last_show_frame = pic_param->show_frame; in hal_vp9d_vdpu34x_gen_regs()
827 hw_ctx->ls_info.last_width = pic_param->width; in hal_vp9d_vdpu34x_gen_regs()
828 hw_ctx->ls_info.last_height = pic_param->height; in hal_vp9d_vdpu34x_gen_regs()
829 hw_ctx->ls_info.last_intra_only = (!pic_param->frame_type || pic_param->intra_only); in hal_vp9d_vdpu34x_gen_regs()
833 hw_ctx->ls_info.last_intra_only); in hal_vp9d_vdpu34x_gen_regs()
839 rcb_buf = p_hal->fast_mode ? hw_ctx->g_buf[task->dec.reg_index].rcb_buf : hw_ctx->rcb_buf; in hal_vp9d_vdpu34x_gen_regs()
840 vdpu34x_setup_rcb(&vp9_hw_regs->common_addr, p_hal->dev, rcb_buf, hw_ctx->rcb_info); in hal_vp9d_vdpu34x_gen_regs()
856 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_vdpu34x_start() local
857 Vdpu34xVp9dRegSet *hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->hw_regs; in hal_vp9d_vdpu34x_start()
862 hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->g_buf[index].hw_regs; in hal_vp9d_vdpu34x_start()
966 vdpu34x_set_rcbinfo(dev, hw_ctx->rcb_info); in hal_vp9d_vdpu34x_start()
983 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_vdpu34x_wait() local
984 Vdpu34xVp9dRegSet *hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->hw_regs; in hal_vp9d_vdpu34x_wait()
987 hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->g_buf[task->dec.reg_index].hw_regs; in hal_vp9d_vdpu34x_wait()
1014 mpp_buffer_sync_end(hw_ctx->count_base); in hal_vp9d_vdpu34x_wait()
1015 hal_vp9d_update_counts(mpp_buffer_get_ptr(hw_ctx->count_base), task->dec.syntax.data); in hal_vp9d_vdpu34x_wait()
1020 hw_ctx->g_buf[task->dec.reg_index].use_flag = 0; in hal_vp9d_vdpu34x_wait()
1030 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_vdpu34x_reset() local
1034 memset(&hw_ctx->ls_info, 0, sizeof(hw_ctx->ls_info)); in hal_vp9d_vdpu34x_reset()
1035 hw_ctx->mv_base_addr = -1; in hal_vp9d_vdpu34x_reset()
1036 hw_ctx->pre_mv_base_addr = -1; in hal_vp9d_vdpu34x_reset()
1037 hw_ctx->last_segid_flag = 1; in hal_vp9d_vdpu34x_reset()
1038 memset(&hw_ctx->prob_ref_poc, 0, sizeof(hw_ctx->prob_ref_poc)); in hal_vp9d_vdpu34x_reset()
1039 hw_ctx->col_ref_poc = 0; in hal_vp9d_vdpu34x_reset()
1040 hw_ctx->segid_ref_poc = 0; in hal_vp9d_vdpu34x_reset()
1050 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx; in hal_vp9d_vdpu34x_flush() local
1054 hw_ctx->mv_base_addr = -1; in hal_vp9d_vdpu34x_flush()
1055 hw_ctx->pre_mv_base_addr = -1; in hal_vp9d_vdpu34x_flush()