41     info[idx].size = buf_size;  in update_size_offset()
70         mpp_assert(info[i].size < (RK_S32)MPP_ALIGN(width * rcb_coeff[i], RCB_ALLINE_SIZE));  in vdpu384a_check_rcb_buf_size()
73         mpp_assert(info[i].size < (RK_S32)MPP_ALIGN(height * rcb_coeff[i], RCB_ALLINE_SIZE));  in vdpu384a_check_rcb_buf_size()
94     reg->reg141_rcb_strmd_row_len            =  info[RCB_STRMD_ROW].size          ;  in vdpu384a_setup_rcb()
95     reg->reg143_rcb_strmd_tile_row_len       =  info[RCB_STRMD_TILE_ROW].size     ;  in vdpu384a_setup_rcb()
96     reg->reg145_rcb_inter_row_len            =  info[RCB_INTER_ROW].size          ;  in vdpu384a_setup_rcb()
97     reg->reg147_rcb_inter_tile_row_len       =  info[RCB_INTER_TILE_ROW].size     ;  in vdpu384a_setup_rcb()
98     reg->reg149_rcb_intra_row_len            =  info[RCB_INTRA_ROW].size          ;  in vdpu384a_setup_rcb()
99     reg->reg151_rcb_intra_tile_row_len       =  info[RCB_INTRA_TILE_ROW].size     ;  in vdpu384a_setup_rcb()
100     reg->reg153_rcb_filterd_row_len          =  info[RCB_FILTERD_ROW].size        ;  in vdpu384a_setup_rcb()
101     reg->reg157_rcb_filterd_tile_row_len     =  info[RCB_FILTERD_TILE_ROW].size   ;  in vdpu384a_setup_rcb()
102     reg->reg159_rcb_filterd_tile_col_len     =  info[RCB_FILTERD_TILE_COL].size   ;  in vdpu384a_setup_rcb()
103     reg->reg161_rcb_filterd_av1_upscale_tile_col_len = info[RCB_FILTERD_AV1_UP_TILE_COL].size;  in vdpu384a_setup_rcb()
117     val = (p0->size > p1->size) ? -1 : 1;  in vdpu384a_compare_rcb_size()
196             rcb_cfg.size = info[i].size;  in vdpu384a_set_rcbinfo()
197             if (rcb_cfg.size > 0) {  in vdpu384a_set_rcbinfo()
211             rcb_cfg.size = info[index].size;  in vdpu384a_set_rcbinfo()
212             if (rcb_cfg.size > 0) {  in vdpu384a_set_rcbinfo()