Lines Matching refs:info
33 static RK_S32 update_size_offset(Vdpu384aRcbInfo *info, RK_U32 reg_idx, in update_size_offset() argument
39 info[idx].reg_idx = reg_idx; in update_size_offset()
40 info[idx].offset = offset; in update_size_offset()
41 info[idx].size = buf_size; in update_size_offset()
46 RK_S32 vdpu384a_get_rcb_buf_size(Vdpu384aRcbInfo *info, RK_S32 width, RK_S32 height) in vdpu384a_get_rcb_buf_size() argument
50 offset += update_size_offset(info, 140, offset, width, RCB_STRMD_ROW); in vdpu384a_get_rcb_buf_size()
51 offset += update_size_offset(info, 142, offset, width, RCB_STRMD_TILE_ROW); in vdpu384a_get_rcb_buf_size()
52 offset += update_size_offset(info, 144, offset, width, RCB_INTER_ROW); in vdpu384a_get_rcb_buf_size()
53 offset += update_size_offset(info, 146, offset, width, RCB_INTER_TILE_ROW); in vdpu384a_get_rcb_buf_size()
54 offset += update_size_offset(info, 148, offset, width, RCB_INTRA_ROW); in vdpu384a_get_rcb_buf_size()
55 offset += update_size_offset(info, 150, offset, width, RCB_INTRA_TILE_ROW); in vdpu384a_get_rcb_buf_size()
56 offset += update_size_offset(info, 152, offset, width, RCB_FILTERD_ROW); in vdpu384a_get_rcb_buf_size()
57 offset += update_size_offset(info, 154, offset, width, RCB_FILTERD_PROTECT_ROW); in vdpu384a_get_rcb_buf_size()
58 offset += update_size_offset(info, 156, offset, width, RCB_FILTERD_TILE_ROW); in vdpu384a_get_rcb_buf_size()
59 offset += update_size_offset(info, 158, offset, height, RCB_FILTERD_TILE_COL); in vdpu384a_get_rcb_buf_size()
60 offset += update_size_offset(info, 160, offset, height, RCB_FILTERD_AV1_UP_TILE_COL); in vdpu384a_get_rcb_buf_size()
65 RK_RET vdpu384a_check_rcb_buf_size(Vdpu384aRcbInfo *info, RK_S32 width, RK_S32 height) in vdpu384a_check_rcb_buf_size() argument
70 mpp_assert(info[i].size < (RK_S32)MPP_ALIGN(width * rcb_coeff[i], RCB_ALLINE_SIZE)); in vdpu384a_check_rcb_buf_size()
73 mpp_assert(info[i].size < (RK_S32)MPP_ALIGN(height * rcb_coeff[i], RCB_ALLINE_SIZE)); in vdpu384a_check_rcb_buf_size()
79 MppBuffer buf, Vdpu384aRcbInfo *info) in vdpu384a_setup_rcb() argument
94 reg->reg141_rcb_strmd_row_len = info[RCB_STRMD_ROW].size ; in vdpu384a_setup_rcb()
95 reg->reg143_rcb_strmd_tile_row_len = info[RCB_STRMD_TILE_ROW].size ; in vdpu384a_setup_rcb()
96 reg->reg145_rcb_inter_row_len = info[RCB_INTER_ROW].size ; in vdpu384a_setup_rcb()
97 reg->reg147_rcb_inter_tile_row_len = info[RCB_INTER_TILE_ROW].size ; in vdpu384a_setup_rcb()
98 reg->reg149_rcb_intra_row_len = info[RCB_INTRA_ROW].size ; in vdpu384a_setup_rcb()
99 reg->reg151_rcb_intra_tile_row_len = info[RCB_INTRA_TILE_ROW].size ; in vdpu384a_setup_rcb()
100 reg->reg153_rcb_filterd_row_len = info[RCB_FILTERD_ROW].size ; in vdpu384a_setup_rcb()
101 reg->reg157_rcb_filterd_tile_row_len = info[RCB_FILTERD_TILE_ROW].size ; in vdpu384a_setup_rcb()
102 reg->reg159_rcb_filterd_tile_col_len = info[RCB_FILTERD_TILE_COL].size ; in vdpu384a_setup_rcb()
103 reg->reg161_rcb_filterd_av1_upscale_tile_col_len = info[RCB_FILTERD_AV1_UP_TILE_COL].size; in vdpu384a_setup_rcb()
106 if (info[i].offset) in vdpu384a_setup_rcb()
107 mpp_dev_set_reg_offset(dev, info[i].reg_idx, info[i].offset); in vdpu384a_setup_rcb()
188 Vdpu384aRcbInfo info[RCB_BUF_COUNT]; in vdpu384a_set_rcbinfo() local
190 memcpy(info, rcb_info, sizeof(info)); in vdpu384a_set_rcbinfo()
191 qsort(info, MPP_ARRAY_ELEMS(info), in vdpu384a_set_rcbinfo()
192 sizeof(info[0]), vdpu384a_compare_rcb_size); in vdpu384a_set_rcbinfo()
194 for (i = 0; i < MPP_ARRAY_ELEMS(info); i++) { in vdpu384a_set_rcbinfo()
195 rcb_cfg.reg_idx = info[i].reg_idx; in vdpu384a_set_rcbinfo()
196 rcb_cfg.size = info[i].size; in vdpu384a_set_rcbinfo()
204 Vdpu384aRcbInfo *info = rcb_info; in vdpu384a_set_rcbinfo() local
210 rcb_cfg.reg_idx = info[index].reg_idx; in vdpu384a_set_rcbinfo()
211 rcb_cfg.size = info[index].size; in vdpu384a_set_rcbinfo()