44                                  RK_S32 offset, RK_S32 len, RK_S32 idx)  in update_size_offset()  argument
50     info[idx].offset = offset;  in update_size_offset()
58     RK_S32 offset = 0;  in vdpu382_get_rcb_buf_size()  local
60     offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW);  in vdpu382_get_rcb_buf_size()
61     offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW);  in vdpu382_get_rcb_buf_size()
62     offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW);  in vdpu382_get_rcb_buf_size()
63     offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW);  in vdpu382_get_rcb_buf_size()
64     offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW);  in vdpu382_get_rcb_buf_size()
65     offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW);  in vdpu382_get_rcb_buf_size()
66     offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW);  in vdpu382_get_rcb_buf_size()
68     offset += update_size_offset(info, 135, offset, height, RCB_TRANSD_COL);  in vdpu382_get_rcb_buf_size()
69     offset += update_size_offset(info, 138, offset, height, RCB_INTER_COL);  in vdpu382_get_rcb_buf_size()
70     offset += update_size_offset(info, 142, offset, height, RCB_FILT_COL);  in vdpu382_get_rcb_buf_size()
72     return offset;  in vdpu382_get_rcb_buf_size()
90     if (info[RCB_DBLK_ROW].offset)  in vdpu382_setup_rcb()
91         mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset);  in vdpu382_setup_rcb()
92     if (info[RCB_INTRA_ROW].offset)  in vdpu382_setup_rcb()
93         mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset);  in vdpu382_setup_rcb()
94     if (info[RCB_TRANSD_ROW].offset)  in vdpu382_setup_rcb()
95         mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset);  in vdpu382_setup_rcb()
96     if (info[RCB_STRMD_ROW].offset)  in vdpu382_setup_rcb()
97         mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset);  in vdpu382_setup_rcb()
98     if (info[RCB_INTER_ROW].offset)  in vdpu382_setup_rcb()
99         mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset);  in vdpu382_setup_rcb()
100     if (info[RCB_SAO_ROW].offset)  in vdpu382_setup_rcb()
101         mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset);  in vdpu382_setup_rcb()
102     if (info[RCB_FBC_ROW].offset)  in vdpu382_setup_rcb()
103         mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset);  in vdpu382_setup_rcb()
104     if (info[RCB_TRANSD_COL].offset)  in vdpu382_setup_rcb()
105         mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset);  in vdpu382_setup_rcb()
106     if (info[RCB_INTER_COL].offset)  in vdpu382_setup_rcb()
107         mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset);  in vdpu382_setup_rcb()
108     if (info[RCB_FILT_COL].offset)  in vdpu382_setup_rcb()
109         mpp_dev_set_reg_offset(dev, 142, info[RCB_FILT_COL].offset);  in vdpu382_setup_rcb()