43 static RK_S32 update_size_offset(Vdpu34xRcbInfo *info, RK_U32 reg,  in update_size_offset()  argument
49     info[idx].reg = reg;  in update_size_offset()
50     info[idx].offset = offset;  in update_size_offset()
51     info[idx].size = buf_size;  in update_size_offset()
56 RK_S32 vdpu34x_get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height)  in vdpu34x_get_rcb_buf_size()  argument
60     offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW);  in vdpu34x_get_rcb_buf_size()
61     offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW);  in vdpu34x_get_rcb_buf_size()
62     offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW);  in vdpu34x_get_rcb_buf_size()
63     offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW);  in vdpu34x_get_rcb_buf_size()
64     offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW);  in vdpu34x_get_rcb_buf_size()
65     offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW);  in vdpu34x_get_rcb_buf_size()
66     offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW);  in vdpu34x_get_rcb_buf_size()
68     offset += update_size_offset(info, 135, offset, height, RCB_TRANSD_COL);  in vdpu34x_get_rcb_buf_size()
69     offset += update_size_offset(info, 138, offset, height, RCB_INTER_COL);  in vdpu34x_get_rcb_buf_size()
70     offset += update_size_offset(info, 142, offset, height, RCB_FILT_COL);  in vdpu34x_get_rcb_buf_size()
75 void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info)  in vdpu34x_setup_rcb()  argument
90     if (info[RCB_DBLK_ROW].offset)  in vdpu34x_setup_rcb()
91         mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset);  in vdpu34x_setup_rcb()
92     if (info[RCB_INTRA_ROW].offset)  in vdpu34x_setup_rcb()
93         mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset);  in vdpu34x_setup_rcb()
94     if (info[RCB_TRANSD_ROW].offset)  in vdpu34x_setup_rcb()
95         mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset);  in vdpu34x_setup_rcb()
96     if (info[RCB_STRMD_ROW].offset)  in vdpu34x_setup_rcb()
97         mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset);  in vdpu34x_setup_rcb()
98     if (info[RCB_INTER_ROW].offset)  in vdpu34x_setup_rcb()
99         mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset);  in vdpu34x_setup_rcb()
100     if (info[RCB_SAO_ROW].offset)  in vdpu34x_setup_rcb()
101         mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset);  in vdpu34x_setup_rcb()
102     if (info[RCB_FBC_ROW].offset)  in vdpu34x_setup_rcb()
103         mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset);  in vdpu34x_setup_rcb()
104     if (info[RCB_TRANSD_COL].offset)  in vdpu34x_setup_rcb()
105         mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset);  in vdpu34x_setup_rcb()
106     if (info[RCB_INTER_COL].offset)  in vdpu34x_setup_rcb()
107         mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset);  in vdpu34x_setup_rcb()
108     if (info[RCB_FILT_COL].offset)  in vdpu34x_setup_rcb()
109         mpp_dev_set_reg_offset(dev, 142, info[RCB_FILT_COL].offset);  in vdpu34x_setup_rcb()
144         Vdpu34xRcbInfo info[RCB_BUF_COUNT];  in vdpu34x_set_rcbinfo()  local
146         memcpy(info, rcb_info, sizeof(info));  in vdpu34x_set_rcbinfo()
147         qsort(info, MPP_ARRAY_ELEMS(info),  in vdpu34x_set_rcbinfo()
148               sizeof(info[0]), vdpu34x_compare_rcb_size);  in vdpu34x_set_rcbinfo()
150         for (i = 0; i < MPP_ARRAY_ELEMS(info); i++) {  in vdpu34x_set_rcbinfo()
151             rcb_cfg.reg_idx = info[i].reg;  in vdpu34x_set_rcbinfo()
152             rcb_cfg.size = info[i].size;  in vdpu34x_set_rcbinfo()
160         Vdpu34xRcbInfo *info = rcb_info;  in vdpu34x_set_rcbinfo()  local
174             rcb_cfg.reg_idx = info[index].reg;  in vdpu34x_set_rcbinfo()
175             rcb_cfg.size = info[index].size;  in vdpu34x_set_rcbinfo()