Lines Matching refs:p_hal
350 static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len) in prepare_spspps() argument
354 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in prepare_spspps()
360 if (!p_hal->fast_mode && !pp->spspps_update) { in prepare_spspps()
445 static MPP_RET prepare_framerps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len) in prepare_framerps() argument
455 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in prepare_framerps()
484 dpb_valid = (p_hal->slice_long[0].RefPicList[0][i].bPicEntry == 0xff) ? 0 : 1; in prepare_framerps()
485 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].Index7Bits : 0; in prepare_framerps()
486 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].AssociatedFlag : 0; in prepare_framerps()
496 dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1; in prepare_framerps()
497 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0; in prepare_framerps()
498 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0; in prepare_framerps()
511 static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len) in prepare_scanlist() argument
515 if (p_hal->pp->scaleing_list_enable_flag) { in prepare_scanlist()
518 data[n++] = p_hal->qm->bScalingLists4x4[i][j]; in prepare_scanlist()
523 data[n++] = p_hal->qm->bScalingLists8x8[i][j]; in prepare_scanlist()
532 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, HalTaskInfo *task) in set_registers() argument
534 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in set_registers()
540 common->reg016_str_len = p_hal->strm_len; in set_registers()
541 common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag; in set_registers()
552 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe); in set_registers()
579 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer); in set_registers()
584 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits); in set_registers()
633 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer); in set_registers()
634 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe); in set_registers()
646 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index); in set_registers()
653 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in set_registers()
655 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer); in set_registers()
660 mpp_dev_set_reg_offset(p_hal->dev, 197, reg_ctx->offset_cabac); in set_registers()
711 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_init() local
713 INP_CHECK(ret, NULL == p_hal); in vdpu34x_h264d_init()
715 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu34xH264dRegCtx))); in vdpu34x_h264d_init()
716 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in vdpu34x_h264d_init()
717 RK_U32 max_cnt = p_hal->fast_mode ? VDPU34X_FAST_REG_SET_CNT : 1; in vdpu34x_h264d_init()
721 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs, in vdpu34x_h264d_init()
735 if (!p_hal->fast_mode) { in vdpu34x_h264d_init()
746 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align); in vdpu34x_h264d_init()
747 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align); in vdpu34x_h264d_init()
748 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align); in vdpu34x_h264d_init()
765 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_deinit() local
766 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in vdpu34x_h264d_deinit()
769 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu34x_h264d_deinit()
776 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1; in vdpu34x_h264d_deinit()
784 if (p_hal->cmv_bufs) { in vdpu34x_h264d_deinit()
785 hal_bufs_deinit(p_hal->cmv_bufs); in vdpu34x_h264d_deinit()
786 p_hal->cmv_bufs = NULL; in vdpu34x_h264d_deinit()
789 MPP_FREE(p_hal->reg_ctx); in vdpu34x_h264d_deinit()
794 static void h264d_refine_rcb_size(H264dHalCtx_t *p_hal, Vdpu34xRcbInfo *rcb_info, in h264d_refine_rcb_size() argument
799 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag; in h264d_refine_rcb_size()
800 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8; in h264d_refine_rcb_size()
801 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc; in h264d_refine_rcb_size()
848 H264dHalCtx_t *p_hal = (H264dHalCtx_t*)hal; in hal_h264d_rcb_info_update() local
849 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag; in hal_h264d_rcb_info_update()
850 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8; in hal_h264d_rcb_info_update()
851 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc; in hal_h264d_rcb_info_update()
852 Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in hal_h264d_rcb_info_update()
853 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64); in hal_h264d_rcb_info_update()
854 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64); in hal_h264d_rcb_info_update()
862 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(ctx->reg_buf) : 1; in hal_h264d_rcb_info_update()
873 mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size); in hal_h264d_rcb_info_update()
890 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_setup_colmv_buf() local
892 RK_U32 colmv_compress = p_hal->pp->frame_mbs_only_flag ? 1 : 0; in vdpu34x_h264d_setup_colmv_buf()
898 if (!p_hal->pp->frame_mbs_only_flag) in vdpu34x_h264d_setup_colmv_buf()
901 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) { in vdpu34x_h264d_setup_colmv_buf()
904 if (p_hal->cmv_bufs) { in vdpu34x_h264d_setup_colmv_buf()
905 hal_bufs_deinit(p_hal->cmv_bufs); in vdpu34x_h264d_setup_colmv_buf()
906 p_hal->cmv_bufs = NULL; in vdpu34x_h264d_setup_colmv_buf()
909 hal_bufs_init(&p_hal->cmv_bufs); in vdpu34x_h264d_setup_colmv_buf()
910 if (p_hal->cmv_bufs == NULL) { in vdpu34x_h264d_setup_colmv_buf()
914 p_hal->mv_size = mv_size; in vdpu34x_h264d_setup_colmv_buf()
915 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots); in vdpu34x_h264d_setup_colmv_buf()
916 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size); in vdpu34x_h264d_setup_colmv_buf()
925 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_gen_regs() local
926 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64); in vdpu34x_h264d_gen_regs()
927 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64); in vdpu34x_h264d_gen_regs()
928 Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in vdpu34x_h264d_gen_regs()
930 INP_CHECK(ret, NULL == p_hal); in vdpu34x_h264d_gen_regs()
933 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu34x_h264d_gen_regs()
937 if (p_hal->fast_mode) { in vdpu34x_h264d_gen_regs()
955 prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps)); in vdpu34x_h264d_gen_regs()
956 prepare_framerps(p_hal, (RK_U64 *)&ctx->rps, sizeof(ctx->rps)); in vdpu34x_h264d_gen_regs()
957 prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst)); in vdpu34x_h264d_gen_regs()
958 set_registers(p_hal, regs, task); in vdpu34x_h264d_gen_regs()
962 if (!p_hal->fast_mode && !p_hal->pp->spspps_update) { in vdpu34x_h264d_gen_regs()
978 mpp_dev_set_reg_offset(p_hal->dev, 161, ctx->spspps_offset); in vdpu34x_h264d_gen_regs()
982 mpp_dev_set_reg_offset(p_hal->dev, 163, ctx->rps_offset); in vdpu34x_h264d_gen_regs()
985 if (p_hal->pp->scaleing_list_enable_flag) { in vdpu34x_h264d_gen_regs()
988 mpp_dev_set_reg_offset(p_hal->dev, 180, ctx->sclst_offset); in vdpu34x_h264d_gen_regs()
993 hal_h264d_rcb_info_update(p_hal, regs); in vdpu34x_h264d_gen_regs()
994 vdpu34x_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ? in vdpu34x_h264d_gen_regs()
1007 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_start() local
1008 INP_CHECK(ret, NULL == p_hal); in vdpu34x_h264d_start()
1011 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu34x_h264d_start()
1015 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in vdpu34x_h264d_start()
1016 Vdpu34xH264dRegSet *regs = p_hal->fast_mode ? in vdpu34x_h264d_start()
1019 MppDev dev = p_hal->dev; in vdpu34x_h264d_start()
1114 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_wait() local
1116 INP_CHECK(ret, NULL == p_hal); in vdpu34x_h264d_wait()
1117 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx; in vdpu34x_h264d_wait()
1118 Vdpu34xH264dRegSet *p_regs = p_hal->fast_mode ? in vdpu34x_h264d_wait()
1123 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu34x_h264d_wait()
1127 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL); in vdpu34x_h264d_wait()
1132 if (p_hal->dec_cb) { in vdpu34x_h264d_wait()
1148 mpp_callback(p_hal->dec_cb, ¶m); in vdpu34x_h264d_wait()
1151 if (p_hal->fast_mode) { in vdpu34x_h264d_wait()
1163 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_reset() local
1165 INP_CHECK(ret, NULL == p_hal); in vdpu34x_h264d_reset()
1175 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_flush() local
1177 INP_CHECK(ret, NULL == p_hal); in vdpu34x_h264d_flush()
1186 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu34x_h264d_control() local
1188 INP_CHECK(ret, NULL == p_hal); in vdpu34x_h264d_control()
1198 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422); in vdpu34x_h264d_control()
1201 vdpu34x_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16); in vdpu34x_h264d_control()
1203 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align_256_odds); in vdpu34x_h264d_control()