Lines Matching refs:val
43 RK_U16 val) in vdpu1_set_refer_pic_idx() argument
47 p_regs->SwReg30.sw_refer0_nbr = val; in vdpu1_set_refer_pic_idx()
50 p_regs->SwReg30.sw_refer1_nbr = val; in vdpu1_set_refer_pic_idx()
53 p_regs->SwReg31.sw_refer2_nbr = val; in vdpu1_set_refer_pic_idx()
56 p_regs->SwReg31.sw_refer3_nbr = val; in vdpu1_set_refer_pic_idx()
59 p_regs->SwReg32.sw_refer4_nbr = val; in vdpu1_set_refer_pic_idx()
62 p_regs->SwReg32.sw_refer5_nbr = val; in vdpu1_set_refer_pic_idx()
65 p_regs->SwReg33.sw_refer6_nbr = val; in vdpu1_set_refer_pic_idx()
68 p_regs->SwReg33.sw_refer7_nbr = val; in vdpu1_set_refer_pic_idx()
71 p_regs->SwReg34.sw_refer8_nbr = val; in vdpu1_set_refer_pic_idx()
74 p_regs->SwReg34.sw_refer9_nbr = val; in vdpu1_set_refer_pic_idx()
77 p_regs->SwReg35.sw_refer10_nbr = val; in vdpu1_set_refer_pic_idx()
80 p_regs->SwReg35.sw_refer11_nbr = val; in vdpu1_set_refer_pic_idx()
83 p_regs->SwReg36.sw_refer12_nbr = val; in vdpu1_set_refer_pic_idx()
86 p_regs->SwReg36.sw_refer13_nbr = val; in vdpu1_set_refer_pic_idx()
89 p_regs->SwReg37.sw_refer14_nbr = val; in vdpu1_set_refer_pic_idx()
92 p_regs->SwReg37.sw_refer15_nbr = val; in vdpu1_set_refer_pic_idx()
102 RK_U16 val) in vdpu1_set_refer_pic_list_p() argument
106 p_regs->SwReg47.sw_pinit_rlist_f0 = val; in vdpu1_set_refer_pic_list_p()
109 p_regs->SwReg47.sw_pinit_rlist_f1 = val; in vdpu1_set_refer_pic_list_p()
112 p_regs->SwReg47.sw_pinit_rlist_f2 = val; in vdpu1_set_refer_pic_list_p()
115 p_regs->SwReg47.sw_pinit_rlist_f3 = val; in vdpu1_set_refer_pic_list_p()
118 p_regs->SwReg10.sw_pinit_rlist_f4 = val; in vdpu1_set_refer_pic_list_p()
121 p_regs->SwReg10.sw_pinit_rlist_f5 = val; in vdpu1_set_refer_pic_list_p()
124 p_regs->SwReg10.sw_pinit_rlist_f6 = val; in vdpu1_set_refer_pic_list_p()
127 p_regs->SwReg10.sw_pinit_rlist_f7 = val; in vdpu1_set_refer_pic_list_p()
130 p_regs->SwReg10.sw_pinit_rlist_f8 = val; in vdpu1_set_refer_pic_list_p()
133 p_regs->SwReg10.sw_pinit_rlist_f9 = val; in vdpu1_set_refer_pic_list_p()
136 p_regs->SwReg11.sw_pinit_rlist_f10 = val; in vdpu1_set_refer_pic_list_p()
139 p_regs->SwReg11.sw_pinit_rlist_f11 = val; in vdpu1_set_refer_pic_list_p()
142 p_regs->SwReg11.sw_pinit_rlist_f12 = val; in vdpu1_set_refer_pic_list_p()
145 p_regs->SwReg11.sw_pinit_rlist_f13 = val; in vdpu1_set_refer_pic_list_p()
148 p_regs->SwReg11.sw_pinit_rlist_f14 = val; in vdpu1_set_refer_pic_list_p()
151 p_regs->SwReg11.sw_pinit_rlist_f15 = val; in vdpu1_set_refer_pic_list_p()
161 RK_U16 val) in vdpu1_set_refer_pic_list_b0() argument
165 p_regs->SwReg42.sw_binit_rlist_f0 = val; in vdpu1_set_refer_pic_list_b0()
168 p_regs->SwReg42.sw_binit_rlist_f1 = val; in vdpu1_set_refer_pic_list_b0()
171 p_regs->SwReg42.sw_binit_rlist_f2 = val; in vdpu1_set_refer_pic_list_b0()
174 p_regs->SwReg43.sw_binit_rlist_f3 = val; in vdpu1_set_refer_pic_list_b0()
177 p_regs->SwReg43.sw_binit_rlist_f4 = val; in vdpu1_set_refer_pic_list_b0()
180 p_regs->SwReg43.sw_binit_rlist_f5 = val; in vdpu1_set_refer_pic_list_b0()
183 p_regs->SwReg44.sw_binit_rlist_f6 = val; in vdpu1_set_refer_pic_list_b0()
186 p_regs->SwReg44.sw_binit_rlist_f7 = val; in vdpu1_set_refer_pic_list_b0()
189 p_regs->SwReg44.sw_binit_rlist_f8 = val; in vdpu1_set_refer_pic_list_b0()
192 p_regs->SwReg45.sw_binit_rlist_f9 = val; in vdpu1_set_refer_pic_list_b0()
195 p_regs->SwReg45.sw_binit_rlist_f10 = val; in vdpu1_set_refer_pic_list_b0()
198 p_regs->SwReg45.sw_binit_rlist_f11 = val; in vdpu1_set_refer_pic_list_b0()
201 p_regs->SwReg46.sw_binit_rlist_f12 = val; in vdpu1_set_refer_pic_list_b0()
204 p_regs->SwReg46.sw_binit_rlist_f13 = val; in vdpu1_set_refer_pic_list_b0()
207 p_regs->SwReg46.sw_binit_rlist_f14 = val; in vdpu1_set_refer_pic_list_b0()
210 p_regs->SwReg47.sw_binit_rlist_f15 = val; in vdpu1_set_refer_pic_list_b0()
220 RK_U16 val) in vdpu1_set_refer_pic_list_b1() argument
224 p_regs->SwReg42.sw_binit_rlist_b0 = val; in vdpu1_set_refer_pic_list_b1()
227 p_regs->SwReg42.sw_binit_rlist_b1 = val; in vdpu1_set_refer_pic_list_b1()
230 p_regs->SwReg42.sw_binit_rlist_b2 = val; in vdpu1_set_refer_pic_list_b1()
233 p_regs->SwReg43.sw_binit_rlist_b3 = val; in vdpu1_set_refer_pic_list_b1()
236 p_regs->SwReg43.sw_binit_rlist_b4 = val; in vdpu1_set_refer_pic_list_b1()
239 p_regs->SwReg43.sw_binit_rlist_b5 = val; in vdpu1_set_refer_pic_list_b1()
242 p_regs->SwReg44.sw_binit_rlist_b6 = val; in vdpu1_set_refer_pic_list_b1()
245 p_regs->SwReg44.sw_binit_rlist_b7 = val; in vdpu1_set_refer_pic_list_b1()
248 p_regs->SwReg44.sw_binit_rlist_b8 = val; in vdpu1_set_refer_pic_list_b1()
251 p_regs->SwReg45.sw_binit_rlist_b9 = val; in vdpu1_set_refer_pic_list_b1()
254 p_regs->SwReg45.sw_binit_rlist_b10 = val; in vdpu1_set_refer_pic_list_b1()
257 p_regs->SwReg45.sw_binit_rlist_b11 = val; in vdpu1_set_refer_pic_list_b1()
260 p_regs->SwReg46.sw_binit_rlist_b12 = val; in vdpu1_set_refer_pic_list_b1()
263 p_regs->SwReg46.sw_binit_rlist_b13 = val; in vdpu1_set_refer_pic_list_b1()
266 p_regs->SwReg46.sw_binit_rlist_b14 = val; in vdpu1_set_refer_pic_list_b1()
269 p_regs->SwReg47.sw_binit_rlist_b15 = val; in vdpu1_set_refer_pic_list_b1()
279 RK_U32 val) in vdpu1_set_refer_pic_base_addr() argument
283 p_regs->SwReg14.sw_refer0_base = val; in vdpu1_set_refer_pic_base_addr()
286 p_regs->SwReg15.sw_refer1_base = val; in vdpu1_set_refer_pic_base_addr()
289 p_regs->SwReg16.sw_refer2_base = val; in vdpu1_set_refer_pic_base_addr()
292 p_regs->SwReg17.sw_refer3_base = val; in vdpu1_set_refer_pic_base_addr()
295 p_regs->SwReg18.sw_refer4_base = val; in vdpu1_set_refer_pic_base_addr()
298 p_regs->SwReg19.sw_refer5_base = val; in vdpu1_set_refer_pic_base_addr()
301 p_regs->SwReg20.sw_refer6_base = val; in vdpu1_set_refer_pic_base_addr()
304 p_regs->SwReg21.sw_refer7_base = val; in vdpu1_set_refer_pic_base_addr()
307 p_regs->SwReg22.sw_refer8_base = val; in vdpu1_set_refer_pic_base_addr()
310 p_regs->SwReg23.sw_refer9_base = val; in vdpu1_set_refer_pic_base_addr()
313 p_regs->SwReg24.sw_refer10_base = val; in vdpu1_set_refer_pic_base_addr()
316 p_regs->SwReg25.sw_refer11_base = val; in vdpu1_set_refer_pic_base_addr()
319 p_regs->SwReg26.sw_refer12_base = val; in vdpu1_set_refer_pic_base_addr()
322 p_regs->SwReg27.sw_refer13_base = val; in vdpu1_set_refer_pic_base_addr()
325 p_regs->SwReg28.sw_refer14_base = val; in vdpu1_set_refer_pic_base_addr()
328 p_regs->SwReg29.sw_refer15_base = val; in vdpu1_set_refer_pic_base_addr()
550 RK_U32 val = 0; in vdpu1_set_asic_regs() local
579 val = top_closer | field_flag; in vdpu1_set_asic_regs()
580 if (val) in vdpu1_set_asic_regs()
581 mpp_dev_set_reg_offset(p_hal->dev, vdpu1_ref_idx[i], val); in vdpu1_set_asic_regs()
721 RK_U32 val = 0; in vdpu1_set_device_regs() local
724 val = (RK_U32)(-5); in vdpu1_set_device_regs()
725 p_reg->SwReg49.sw_pred_bc_tap_0_1 = val; in vdpu1_set_device_regs()