Lines Matching refs:p_hal
336 static MPP_RET vdpu1_set_pic_regs(H264dHalCtx_t *p_hal, in vdpu1_set_pic_regs() argument
341 p_regs->SwReg04.sw_pic_mb_width = p_hal->pp->wFrameWidthInMbsMinus1 + 1; in vdpu1_set_pic_regs()
342 p_regs->SwReg04.sw_pic_mb_height_p = (2 - p_hal->pp->frame_mbs_only_flag) in vdpu1_set_pic_regs()
343 * (p_hal->pp->wFrameHeightInMbsMinus1 + 1); in vdpu1_set_pic_regs()
348 static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal, in vdpu1_set_vlc_regs() argument
353 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in vdpu1_set_vlc_regs()
368 p_regs->SwReg08.sw_refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen; in vdpu1_set_vlc_regs()
369 p_regs->SwReg08.sw_idr_pic_e = p_hal->slice_long[0].idr_flag; in vdpu1_set_vlc_regs()
370 p_regs->SwReg08.sw_idr_pic_id = p_hal->slice_long[0].idr_pic_id; in vdpu1_set_vlc_regs()
372 p_regs->SwReg09.sw_pps_id = p_hal->slice_long[0].active_pps_id; in vdpu1_set_vlc_regs()
373 p_regs->SwReg09.sw_poc_length = p_hal->slice_long[0].poc_used_bitlen; in vdpu1_set_vlc_regs()
423 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_set_vlc_regs()
454 mpp_buf_slot_get_prop(p_hal->packet_slots, p_hal->in_task->input, in vdpu1_set_vlc_regs()
460 p_regs->SwReg06.sw_stream_len = p_hal->strm_len; in vdpu1_set_vlc_regs()
466 static MPP_RET vdpu1_set_ref_regs(H264dHalCtx_t *p_hal, in vdpu1_set_ref_regs() argument
474 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in vdpu1_set_ref_regs()
523 if (num_refs > 1 && !p_hal->pp->field_pic_flag) { in vdpu1_set_ref_regs()
538 static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal, in vdpu1_set_asic_regs() argument
545 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in vdpu1_set_asic_regs()
546 DXVA_Slice_H264_Long *p_long = &p_hal->slice_long[0]; in vdpu1_set_asic_regs()
557 mpp_buf_slot_get_prop(p_hal->frame_slots, in vdpu1_set_asic_regs()
562 mpp_buf_slot_get_prop(p_hal->frame_slots, in vdpu1_set_asic_regs()
581 mpp_dev_set_reg_offset(p_hal->dev, vdpu1_ref_idx[i], val); in vdpu1_set_asic_regs()
587 H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv; in vdpu1_set_asic_regs()
589 mpp_buf_slot_get_prop(p_hal->frame_slots, in vdpu1_set_asic_regs()
601 mpp_buf_slot_get_prop(p_hal->frame_slots, in vdpu1_set_asic_regs()
606 mpp_dev_set_reg_offset(p_hal->dev, 13, ((pp->wFrameWidthInMbsMinus1 + 1) * 16)); in vdpu1_set_asic_regs()
618 picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1; in vdpu1_set_asic_regs()
622 * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384); in vdpu1_set_asic_regs()
627 mpp_dev_set_reg_offset(p_hal->dev, 41, offset); in vdpu1_set_asic_regs()
651 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_set_asic_regs()
652 if (p_hal->pp->scaleing_list_enable_flag) { in vdpu1_set_asic_regs()
658 temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) | in vdpu1_set_asic_regs()
659 (p_hal->qm->bScalingLists4x4[i][4 * j + 1] << 16) | in vdpu1_set_asic_regs()
660 (p_hal->qm->bScalingLists4x4[i][4 * j + 2] << 8) | in vdpu1_set_asic_regs()
661 (p_hal->qm->bScalingLists4x4[i][4 * j + 3]); in vdpu1_set_asic_regs()
668 temp = (p_hal->qm->bScalingLists8x8[i][4 * j + 0] << 24) | in vdpu1_set_asic_regs()
669 (p_hal->qm->bScalingLists8x8[i][4 * j + 1] << 16) | in vdpu1_set_asic_regs()
670 (p_hal->qm->bScalingLists8x8[i][4 * j + 2] << 8) | in vdpu1_set_asic_regs()
671 (p_hal->qm->bScalingLists8x8[i][4 * j + 3]); in vdpu1_set_asic_regs()
686 static MPP_RET vdpu1_set_device_regs(H264dHalCtx_t *p_hal, in vdpu1_set_device_regs() argument
729 (void)p_hal; in vdpu1_set_device_regs()
744 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_init() local
749 MEM_CHECK(ret, p_hal->priv = in vdpu1_h264d_init()
752 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t))); in vdpu1_h264d_init()
753 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_h264d_init()
757 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu1_h264d_init()
761 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->reg_buf[i].buf, buf_size)); in vdpu1_h264d_init()
770 if (!p_hal->fast_mode) { in vdpu1_h264d_init()
778 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align); in vdpu1_h264d_init()
779 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align); in vdpu1_h264d_init()
798 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_deinit() local
799 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_h264d_deinit()
802 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu1_h264d_deinit()
807 MPP_FREE(p_hal->reg_ctx); in vdpu1_h264d_deinit()
808 MPP_FREE(p_hal->priv); in vdpu1_h264d_deinit()
825 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_gen_regs() local
826 INP_CHECK(ret, NULL == p_hal); in vdpu1_h264d_gen_regs()
827 p_hal->in_task = &task->dec; in vdpu1_h264d_gen_regs()
829 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu1_h264d_gen_regs()
832 priv = p_hal->priv; in vdpu1_h264d_gen_regs()
833 priv->layed_id = p_hal->pp->curr_layer_id; in vdpu1_h264d_gen_regs()
835 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_h264d_gen_regs()
836 if (p_hal->fast_mode) { in vdpu1_h264d_gen_regs()
852 FUN_CHECK(ret = adjust_input(priv, &p_hal->slice_long[0], p_hal->pp)); in vdpu1_h264d_gen_regs()
853 FUN_CHECK(ret = vdpu1_set_device_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs)); in vdpu1_h264d_gen_regs()
854 FUN_CHECK(ret = vdpu1_set_pic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs)); in vdpu1_h264d_gen_regs()
855 FUN_CHECK(ret = vdpu1_set_vlc_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs)); in vdpu1_h264d_gen_regs()
856 FUN_CHECK(ret = vdpu1_set_ref_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs)); in vdpu1_h264d_gen_regs()
857 FUN_CHECK(ret = vdpu1_set_asic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs)); in vdpu1_h264d_gen_regs()
876 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_start() local
877 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_h264d_start()
878 H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ? in vdpu1_h264d_start()
883 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu1_h264d_start()
903 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu1_h264d_start()
913 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu1_h264d_start()
919 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_SEND, NULL); in vdpu1_h264d_start()
941 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_wait() local
942 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu1_h264d_wait()
943 H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ? in vdpu1_h264d_wait()
948 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu1_h264d_wait()
952 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL); in vdpu1_h264d_wait()
957 if (p_hal->dec_cb) { in vdpu1_h264d_wait()
964 mpp_callback(p_hal->dec_cb, ¶m); in vdpu1_h264d_wait()
967 if (p_hal->fast_mode) { in vdpu1_h264d_wait()
985 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_reset() local
987 INP_CHECK(ret, NULL == p_hal); in vdpu1_h264d_reset()
988 memset(p_hal->priv, 0, sizeof(H264dVdpuPriv_t)); in vdpu1_h264d_reset()
1004 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_flush() local
1006 INP_CHECK(ret, NULL == p_hal); in vdpu1_h264d_flush()
1024 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu1_h264d_control() local
1026 INP_CHECK(ret, NULL == p_hal); in vdpu1_h264d_control()