Lines Matching refs:H264dVdpu1Regs_t

42 static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i,  in vdpu1_set_refer_pic_idx()
101 static MPP_RET vdpu1_set_refer_pic_list_p(H264dVdpu1Regs_t *p_regs, RK_U32 i,  in vdpu1_set_refer_pic_list_p()
160 static MPP_RET vdpu1_set_refer_pic_list_b0(H264dVdpu1Regs_t *p_regs, RK_U32 i,  in vdpu1_set_refer_pic_list_b0()
219 static MPP_RET vdpu1_set_refer_pic_list_b1(H264dVdpu1Regs_t *p_regs, RK_U32 i,  in vdpu1_set_refer_pic_list_b1()
278 static MPP_RET vdpu1_set_refer_pic_base_addr(H264dVdpu1Regs_t *p_regs, RK_U32 i,  in vdpu1_set_refer_pic_base_addr()
337                                   H264dVdpu1Regs_t *p_regs)  in vdpu1_set_pic_regs()
349                                   H264dVdpu1Regs_t *p_regs)  in vdpu1_set_vlc_regs()
467                                   H264dVdpu1Regs_t *p_regs)  in vdpu1_set_ref_regs()
539                                    H264dVdpu1Regs_t *p_regs)  in vdpu1_set_asic_regs()
687                                      H264dVdpu1Regs_t *p_reg)  in vdpu1_set_device_regs()
765             reg_ctx->reg_buf[i].regs = mpp_calloc_size(void, sizeof(H264dVdpu1Regs_t));  in vdpu1_h264d_init()
853     FUN_CHECK(ret = vdpu1_set_device_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
854     FUN_CHECK(ret = vdpu1_set_pic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
855     FUN_CHECK(ret = vdpu1_set_vlc_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
856     FUN_CHECK(ret = vdpu1_set_ref_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
857     FUN_CHECK(ret = vdpu1_set_asic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));  in vdpu1_h264d_gen_regs()
878     H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ?  in vdpu1_h264d_start()
943     H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ?  in vdpu1_h264d_wait()