1503         RK_U32 mapped_idx = 0;  in prepare_uncompress_header()  local
1509             mapped_idx = dxva->ref_frame_idx[i];  in prepare_uncompress_header()
1510             mpp_put_bits(&bp, dxva->ref_order_hint[mapped_idx], 8);  in prepare_uncompress_header()
1738         RK_U32 mapped_idx = 0;  in prepare_uncompress_header()  local
1743             mapped_idx = dxva->ref_frame_idx[i];  in prepare_uncompress_header()
1744             mapped_frame_width[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_width;  in prepare_uncompress_header()
1745             mapped_frame_height[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_height;  in prepare_uncompress_header()
2076     RK_U32 mapped_idx = 0;  in vdpu383_av1d_set_cdf()  local
2111         mapped_idx = dxva->ref_frame_idx[dxva->primary_ref_frame];  in vdpu383_av1d_set_cdf()
2113         coeff_cdf_idx = reg_ctx->ref_info_tbl[mapped_idx].coeff_idx;  in vdpu383_av1d_set_cdf()
2115             reg_ctx->ref_info_tbl[mapped_idx].cdf_valid &&  in vdpu383_av1d_set_cdf()
2116             dxva->frame_refs[mapped_idx].Index != (CHAR)0xff &&  in vdpu383_av1d_set_cdf()
2117             dxva->frame_refs[mapped_idx].Index != 0x7f) {  in vdpu383_av1d_set_cdf()
2118             cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_segid_bufs, dxva->frame_refs[mapped_idx].Index);  in vdpu383_av1d_set_cdf()
2330         RK_U32 mapped_idx;  in vdpu383_av1d_gen_regs()  local
2365             mapped_idx = dxva->ref_frame_idx[i];  in vdpu383_av1d_gen_regs()
2366 …if (dxva->frame_refs[mapped_idx].Index != (CHAR)0xff && dxva->frame_refs[mapped_idx].Index != 0x7f…  in vdpu383_av1d_gen_regs()
2367 …  mpp_buf_slot_get_prop(p_hal->slots, dxva->frame_refs[mapped_idx].Index, SLOT_FRAME_PTR, &mframe);  in vdpu383_av1d_gen_regs()
2378                     SET_REF_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);  in vdpu383_av1d_gen_regs()
2379 …                 SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);  in vdpu383_av1d_gen_regs()
2380                     SET_REF_VIRSTRIDE(regs->av1d_paras, mapped_idx, y_virstride >> 4);  in vdpu383_av1d_gen_regs()
2389         RK_U32 mapped_idx;  in vdpu383_av1d_gen_regs()  local
2397             mapped_idx = dxva->ref_frame_idx[i];  in vdpu383_av1d_gen_regs()
2398 …if (dxva->frame_refs[mapped_idx].Index != (CHAR)0xff && dxva->frame_refs[mapped_idx].Index != 0x7f…  in vdpu383_av1d_gen_regs()
2399 …    mpp_buf_slot_get_prop(p_hal->slots, dxva->frame_refs[mapped_idx].Index, SLOT_BUFFER, &mbuffer);  in vdpu383_av1d_gen_regs()
2401 …               origin_buf = hal_bufs_get_buf(ctx->origin_bufs, dxva->frame_refs[mapped_idx].Index);  in vdpu383_av1d_gen_regs()
2405                     SET_REF_BASE(regs->av1d_addrs, mapped_idx, mpp_buffer_get_fd(mbuffer));  in vdpu383_av1d_gen_regs()
2406 …                SET_FBC_PAYLOAD_REF_BASE(regs->av1d_addrs, mapped_idx, mpp_buffer_get_fd(mbuffer));  in vdpu383_av1d_gen_regs()