Lines Matching defs:fsl_ddr_cfg_regs_s

242 typedef struct fsl_ddr_cfg_regs_s {  struct
243 	struct {
247 	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
248 	unsigned int timing_cfg_3;
249 	unsigned int timing_cfg_0;
250 	unsigned int timing_cfg_1;
251 	unsigned int timing_cfg_2;
252 	unsigned int ddr_sdram_cfg;
253 	unsigned int ddr_sdram_cfg_2;
254 	unsigned int ddr_sdram_cfg_3;
255 	unsigned int ddr_sdram_mode;
256 	unsigned int ddr_sdram_mode_2;
257 	unsigned int ddr_sdram_mode_3;
258 	unsigned int ddr_sdram_mode_4;
259 	unsigned int ddr_sdram_mode_5;
260 	unsigned int ddr_sdram_mode_6;
261 	unsigned int ddr_sdram_mode_7;
262 	unsigned int ddr_sdram_mode_8;
263 	unsigned int ddr_sdram_mode_9;
264 	unsigned int ddr_sdram_mode_10;
265 	unsigned int ddr_sdram_mode_11;
266 	unsigned int ddr_sdram_mode_12;
267 	unsigned int ddr_sdram_mode_13;
268 	unsigned int ddr_sdram_mode_14;
269 	unsigned int ddr_sdram_mode_15;
270 	unsigned int ddr_sdram_mode_16;
271 	unsigned int ddr_sdram_md_cntl;
272 	unsigned int ddr_sdram_interval;
273 	unsigned int ddr_data_init;
274 	unsigned int ddr_sdram_clk_cntl;
275 	unsigned int ddr_init_addr;
276 	unsigned int ddr_init_ext_addr;
277 	unsigned int timing_cfg_4;
278 	unsigned int timing_cfg_5;
279 	unsigned int timing_cfg_6;
280 	unsigned int timing_cfg_7;
281 	unsigned int timing_cfg_8;
282 	unsigned int timing_cfg_9;
283 	unsigned int ddr_zq_cntl;
284 	unsigned int ddr_wrlvl_cntl;
285 	unsigned int ddr_wrlvl_cntl_2;
286 	unsigned int ddr_wrlvl_cntl_3;
287 	unsigned int ddr_sr_cntr;
288 	unsigned int ddr_sdram_rcw_1;
289 	unsigned int ddr_sdram_rcw_2;
290 	unsigned int ddr_sdram_rcw_3;
291 	unsigned int ddr_sdram_rcw_4;
292 	unsigned int ddr_sdram_rcw_5;
293 	unsigned int ddr_sdram_rcw_6;
294 	unsigned int dq_map_0;
295 	unsigned int dq_map_1;
296 	unsigned int dq_map_2;
297 	unsigned int dq_map_3;
298 	unsigned int ddr_eor;
299 	unsigned int ddr_cdr1;
300 	unsigned int ddr_cdr2;
301 	unsigned int err_disable;
302 	unsigned int err_int_en;
303 	unsigned int debug[64];