Lines Matching refs:tegra_dc_dp_dpcd_read

327 static int tegra_dc_dp_dpcd_read(struct tegra_dp_priv *dp, u32 cmd,  in tegra_dc_dp_dpcd_read()  function
665 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
676 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
682 	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL,  in tegra_dc_dp_init_max_link_cfg()
686 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE,  in tegra_dc_dp_init_max_link_cfg()
699 	ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
778 		ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ?  in tegra_dc_dp_link_trained()
806 		ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data);  in tegra_dp_channel_eq_status()
828 		ret = tegra_dc_dp_dpcd_read(dp,  in tegra_dp_channel_eq_status()
849 		ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt),  in tegra_dp_clock_recovery_status()
875 		ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt,  in tegra_dp_lt_adjust()
891 		ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2,  in tegra_dp_lt_adjust()
939 	ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data);  in tegra_dp_link_config()
1412 	ret = tegra_dc_dp_dpcd_read(dp, DP_SINK_STATUS, &dpcd_data);  in tegra_dc_dp_sink_out_of_sync()
1531 	if (tegra_dc_dp_dpcd_read(priv, DP_DPCD_REV, &priv->revision)) {  in tegra_dp_enable()