866 			      u32 pc[4], u8 pc_supported,  in tegra_dp_lt_adjust()
896 			pc[cnt] = (data_ptr >>  in tegra_dp_lt_adjust()
1009 			      u32 pc[4], const struct tegra_dp_link_config *cfg)  in tegra_dp_lt_config()
1044 		pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1045 		vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1046 		pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1073 			u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]);  in tegra_dp_lt_config()
1074 			u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]);  in tegra_dp_lt_config()
1075 			val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) |  in tegra_dp_lt_config()
1079 				(pc[cnt + 1] <<  in tegra_dp_lt_config()
1094 				u32 vs[4], u32 pc[4], u8 pc_supported,  in _tegra_dp_channel_eq()
1104 			ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported,  in _tegra_dp_channel_eq()
1108 			tegra_dp_lt_config(dp, pe, vs, pc, cfg);  in _tegra_dp_channel_eq()
1126 			       u32 pc[4],  in tegra_dp_channel_eq()
1139 	ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg);  in tegra_dp_channel_eq()
1147 				  u32 vs[4], u32 pc[4], u8 pc_supported,  in _tegra_dp_clk_recovery()
1155 		tegra_dp_lt_config(dp, pe, vs, pc, cfg);  in _tegra_dp_clk_recovery()
1162 		tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, cfg);  in _tegra_dp_clk_recovery()
1174 				 u32 vs[4], u32 pc[4],  in tegra_dp_clk_recovery()
1183 	err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes,  in tegra_dp_clk_recovery()
1197 	u32 pe[4], vs[4], pc[4];  in tegra_dc_dp_full_link_training()  local
1204 	memset(pc, POSTCURSOR2_LEVEL0, sizeof(pc));  in tegra_dc_dp_full_link_training()
1206 	err = tegra_dp_clk_recovery(dp, pe, vs, pc, cfg);  in tegra_dc_dp_full_link_training()
1215 	err = tegra_dp_channel_eq(dp, pe, vs, pc, cfg);  in tegra_dc_dp_full_link_training()