44 static inline u32 tegra_dpaux_readl(struct tegra_dp_priv *dp, u32 reg)  in tegra_dpaux_readl()  argument
46 	return readl((u32 *)dp->regs + reg);  in tegra_dpaux_readl()
49 static inline void tegra_dpaux_writel(struct tegra_dp_priv *dp, u32 reg,  in tegra_dpaux_writel()  argument
52 	writel(val, (u32 *)dp->regs + reg);  in tegra_dpaux_writel()
55 static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dp_priv *dp,  in tegra_dc_dpaux_poll_register()  argument
65 		reg_val = tegra_dpaux_readl(dp, reg);  in tegra_dc_dpaux_poll_register()
79 static inline int tegra_dpaux_wait_transaction(struct tegra_dp_priv *dp)  in tegra_dpaux_wait_transaction()  argument
83 	if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,  in tegra_dpaux_wait_transaction()
93 static int tegra_dc_dpaux_write_chunk(struct tegra_dp_priv *dp, u32 cmd,  in tegra_dc_dpaux_write_chunk()  argument
117 	tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);  in tegra_dc_dpaux_write_chunk()
120 		tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data);  in tegra_dc_dpaux_write_chunk()
124 	reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);  in tegra_dc_dpaux_write_chunk()
136 		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);  in tegra_dc_dpaux_write_chunk()
138 		if (tegra_dpaux_wait_transaction(dp))  in tegra_dc_dpaux_write_chunk()
141 		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);  in tegra_dc_dpaux_write_chunk()
151 				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,  in tegra_dc_dpaux_write_chunk()
167 				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,  in tegra_dc_dpaux_write_chunk()
190 static int tegra_dc_dpaux_read_chunk(struct tegra_dp_priv *dp, u32 cmd,  in tegra_dc_dpaux_read_chunk()  argument
215 	*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);  in tegra_dc_dpaux_read_chunk()
221 	tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);  in tegra_dc_dpaux_read_chunk()
223 	reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);  in tegra_dc_dpaux_read_chunk()
234 		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);  in tegra_dc_dpaux_read_chunk()
236 		if (tegra_dpaux_wait_transaction(dp))  in tegra_dc_dpaux_read_chunk()
239 		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);  in tegra_dc_dpaux_read_chunk()
249 				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,  in tegra_dc_dpaux_read_chunk()
265 				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,  in tegra_dc_dpaux_read_chunk()
281 				temp_data[i] = tegra_dpaux_readl(dp,  in tegra_dc_dpaux_read_chunk()
299 static int tegra_dc_dpaux_read(struct tegra_dp_priv *dp, u32 cmd, u32 addr,  in tegra_dc_dpaux_read()  argument
311 		ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,  in tegra_dc_dpaux_read()
327 static int tegra_dc_dp_dpcd_read(struct tegra_dp_priv *dp, u32 cmd,  in tegra_dc_dp_dpcd_read()  argument
334 	ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,  in tegra_dc_dp_dpcd_read()
344 static int tegra_dc_dp_dpcd_write(struct tegra_dp_priv *dp, u32 cmd,  in tegra_dc_dp_dpcd_write()  argument
351 	ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,  in tegra_dc_dp_dpcd_write()
361 static int tegra_dc_i2c_aux_read(struct tegra_dp_priv *dp, u32 i2c_addr,  in tegra_dc_i2c_aux_read()  argument
372 				dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr,  in tegra_dc_i2c_aux_read()
381 				dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr,  in tegra_dc_i2c_aux_read()
397 static void tegra_dc_dpaux_enable(struct tegra_dp_priv *dp)  in tegra_dc_dpaux_enable()  argument
400 	tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);  in tegra_dc_dpaux_enable()
402 	tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);  in tegra_dc_dpaux_enable()
404 	tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,  in tegra_dc_dpaux_enable()
410 	tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE,  in tegra_dc_dpaux_enable()
415 static void tegra_dc_dp_dump_link_cfg(struct tegra_dp_priv *dp,  in tegra_dc_dp_dump_link_cfg()  argument
452 static int _tegra_dp_lower_link_config(struct tegra_dp_priv *dp,  in _tegra_dp_lower_link_config()  argument
484 static int tegra_dc_dp_calc_config(struct tegra_dp_priv *dp,  in tegra_dc_dp_calc_config()  argument
648 	tegra_dc_dp_dump_link_cfg(dp, link_cfg);  in tegra_dc_dp_calc_config()
656 			struct tegra_dp_priv *dp,  in tegra_dc_dp_init_max_link_cfg()  argument
665 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
676 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
682 	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL,  in tegra_dc_dp_init_max_link_cfg()
686 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE,  in tegra_dc_dp_init_max_link_cfg()
699 	ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
715 	tegra_dc_dp_calc_config(dp, timing, link_cfg);  in tegra_dc_dp_init_max_link_cfg()
738 static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp,  in tegra_dp_set_link_bandwidth()  argument
745 	return tegra_dc_dp_dpcd_write(dp, DP_LINK_BW_SET, link_bw);  in tegra_dp_set_link_bandwidth()
748 static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp,  in tegra_dp_set_lane_count()  argument
759 	ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data);  in tegra_dp_set_lane_count()
769 static int tegra_dc_dp_link_trained(struct tegra_dp_priv *dp,  in tegra_dc_dp_link_trained()  argument
778 		ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ?  in tegra_dc_dp_link_trained()
796 static int tegra_dp_channel_eq_status(struct tegra_dp_priv *dp,  in tegra_dp_channel_eq_status()  argument
806 		ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data);  in tegra_dp_channel_eq_status()
828 		ret = tegra_dc_dp_dpcd_read(dp,  in tegra_dp_channel_eq_status()
840 static int tegra_dp_clock_recovery_status(struct tegra_dp_priv *dp,  in tegra_dp_clock_recovery_status()  argument
849 		ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt),  in tegra_dp_clock_recovery_status()
865 static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],  in tegra_dp_lt_adjust()  argument
875 		ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt,  in tegra_dp_lt_adjust()
891 		ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2,  in tegra_dp_lt_adjust()
905 static void tegra_dp_wait_aux_training(struct tegra_dp_priv *dp,  in tegra_dp_wait_aux_training()  argument
915 static void tegra_dp_tpg(struct tegra_dp_priv *dp, u32 tp, u32 n_lanes,  in tegra_dp_tpg()  argument
922 	tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg);  in tegra_dp_tpg()
923 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, data);  in tegra_dp_tpg()
926 static int tegra_dp_link_config(struct tegra_dp_priv *dp,  in tegra_dp_link_config()  argument
939 	ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data);  in tegra_dp_link_config()
948 			ret = tegra_dc_dp_dpcd_write(dp, DP_SET_POWER,  in tegra_dp_link_config()
961 		ret = tegra_dc_dp_set_assr(dp, dp->sor, 1);  in tegra_dp_link_config()
966 	ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw);  in tegra_dp_link_config()
971 	ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor);  in tegra_dp_link_config()
976 	tegra_dc_sor_set_dp_linkctl(dp->sor, 1, training_pattern_none,  in tegra_dp_link_config()
982 static int tegra_dp_lower_link_config(struct tegra_dp_priv *dp,  in tegra_dp_lower_link_config()  argument
992 	ret = _tegra_dp_lower_link_config(dp, cfg);  in tegra_dp_lower_link_config()
994 		ret = tegra_dc_dp_calc_config(dp, timing, cfg);  in tegra_dp_lower_link_config()
996 		ret = tegra_dp_link_config(dp, cfg);  in tegra_dp_lower_link_config()
1004 	tegra_dp_link_config(dp, &tmp_cfg);  in tegra_dp_lower_link_config()
1008 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],  in tegra_dp_lt_config()  argument
1011 	struct udevice *sor = dp->sor;  in tegra_dp_lt_config()
1053 	tegra_dp_disable_tx_pu(dp->sor);  in tegra_dp_lt_config()
1068 		tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val);  in tegra_dp_lt_config()
1084 			tegra_dc_dp_dpcd_write(dp,  in tegra_dp_lt_config()
1093 static int _tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4],  in _tegra_dp_channel_eq()  argument
1104 			ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported,  in _tegra_dp_channel_eq()
1108 			tegra_dp_lt_config(dp, pe, vs, pc, cfg);  in _tegra_dp_channel_eq()
1111 		tegra_dp_wait_aux_training(dp, false, cfg);  in _tegra_dp_channel_eq()
1113 		if (!tegra_dp_clock_recovery_status(dp, cfg)) {  in _tegra_dp_channel_eq()
1118 		if (!tegra_dp_channel_eq_status(dp, cfg))  in _tegra_dp_channel_eq()
1125 static int tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],  in tegra_dp_channel_eq()  argument
1137 	tegra_dp_tpg(dp, tp_src, n_lanes, cfg);  in tegra_dp_channel_eq()
1139 	ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg);  in tegra_dp_channel_eq()
1141 	tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg);  in tegra_dp_channel_eq()
1146 static int _tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4],  in _tegra_dp_clk_recovery()  argument
1155 		tegra_dp_lt_config(dp, pe, vs, pc, cfg);  in _tegra_dp_clk_recovery()
1156 		tegra_dp_wait_aux_training(dp, true, cfg);  in _tegra_dp_clk_recovery()
1158 		if (tegra_dp_clock_recovery_status(dp, cfg))  in _tegra_dp_clk_recovery()
1162 		tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, cfg);  in _tegra_dp_clk_recovery()
1173 static int tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4],  in tegra_dp_clk_recovery()  argument
1181 	tegra_dp_tpg(dp, training_pattern_1, n_lanes, cfg);  in tegra_dp_clk_recovery()
1183 	err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes,  in tegra_dp_clk_recovery()
1186 		tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg);  in tegra_dp_clk_recovery()
1191 static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp,  in tegra_dc_dp_full_link_training()  argument
1195 	struct udevice *sor = dp->sor;  in tegra_dc_dp_full_link_training()
1206 	err = tegra_dp_clk_recovery(dp, pe, vs, pc, cfg);  in tegra_dc_dp_full_link_training()
1208 		if (!tegra_dp_lower_link_config(dp, timing, cfg))  in tegra_dc_dp_full_link_training()
1215 	err = tegra_dp_channel_eq(dp, pe, vs, pc, cfg);  in tegra_dc_dp_full_link_training()
1217 		if (!tegra_dp_lower_link_config(dp, timing, cfg))  in tegra_dc_dp_full_link_training()
1224 	tegra_dc_dp_dump_link_cfg(dp, cfg);  in tegra_dc_dp_full_link_training()
1236 static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp,  in tegra_dc_dp_fast_link_training()  argument
1250 	tegra_dc_dp_dpcd_write(dp, DP_MAIN_LINK_CHANNEL_CODING_SET,  in tegra_dc_dp_fast_link_training()
1255 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET,  in tegra_dc_dp_fast_link_training()
1259 		tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24);  in tegra_dc_dp_fast_link_training()
1263 	tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,  in tegra_dc_dp_fast_link_training()
1273 	tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena);  in tegra_dc_dp_fast_link_training()
1276 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET,  in tegra_dc_dp_fast_link_training()
1279 		tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24);  in tegra_dc_dp_fast_link_training()
1283 	tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, DP_LANE0_1_STATUS,  in tegra_dc_dp_fast_link_training()
1292 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, 0);  in tegra_dc_dp_fast_link_training()
1294 	if (tegra_dc_dp_link_trained(dp, link_cfg)) {  in tegra_dc_dp_fast_link_training()
1307 static int tegra_dp_do_link_training(struct tegra_dp_priv *dp,  in tegra_dp_do_link_training()  argument
1317 		ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor);  in tegra_dp_do_link_training()
1325 			ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg);  in tegra_dp_do_link_training()
1334 		ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg);  in tegra_dp_do_link_training()
1351 static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp,  in tegra_dc_dp_explore_link_cfg()  argument
1378 	if ((!tegra_dc_dp_calc_config(dp, timing, &temp_cfg)) &&  in tegra_dc_dp_explore_link_cfg()
1379 	    (!tegra_dp_link_config(dp, &temp_cfg)) &&  in tegra_dc_dp_explore_link_cfg()
1380 		(!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor)))  in tegra_dc_dp_explore_link_cfg()
1387 static int tegra_dp_hpd_plug(struct tegra_dp_priv *dp)  in tegra_dp_hpd_plug()  argument
1395 		val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);  in tegra_dp_hpd_plug()
1404 static int tegra_dc_dp_sink_out_of_sync(struct tegra_dp_priv *dp, u32 delay_ms)  in tegra_dc_dp_sink_out_of_sync()  argument
1412 	ret = tegra_dc_dp_dpcd_read(dp, DP_SINK_STATUS, &dpcd_data);  in tegra_dc_dp_sink_out_of_sync()
1425 static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp,  in tegra_dc_dp_check_sink()  argument
1444 		if (!tegra_dc_dp_sink_out_of_sync(dp, link_cfg->frame_in_ms *  in tegra_dc_dp_check_sink()
1453 		ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor);  in tegra_dc_dp_check_sink()
1456 		if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,  in tegra_dc_dp_check_sink()
1462 		tegra_dc_sor_set_power_state(dp->sor, 1);  in tegra_dc_dp_check_sink()
1463 		tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);  in tegra_dc_dp_check_sink()