799 	u32 cnt;  in tegra_dp_channel_eq_status()  local
805 	for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_channel_eq_status()
806 		ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data);  in tegra_dp_channel_eq_status()
843 	u32 cnt;  in tegra_dp_clock_recovery_status()  local
848 	for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_clock_recovery_status()
849 		ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt),  in tegra_dp_clock_recovery_status()
869 	size_t cnt;  in tegra_dp_lt_adjust()  local
874 	for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_lt_adjust()
875 		ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt,  in tegra_dp_lt_adjust()
879 		pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>  in tegra_dp_lt_adjust()
881 		vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >>  in tegra_dp_lt_adjust()
883 		pe[1 + 2 * cnt] =  in tegra_dp_lt_adjust()
886 		vs[1 + 2 * cnt] =  in tegra_dp_lt_adjust()
895 		for (cnt = 0; cnt < n_lanes; cnt++) {  in tegra_dp_lt_adjust()
896 			pc[cnt] = (data_ptr >>  in tegra_dp_lt_adjust()
897 			NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt)) &  in tegra_dp_lt_adjust()
1014 	u32 cnt;  in tegra_dp_lt_config()  local
1017 	for (cnt = 0; cnt < n_lanes; cnt++) {  in tegra_dp_lt_config()
1022 		switch (cnt) {  in tegra_dp_lt_config()
1044 		pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1045 		vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1046 		pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]];  in tegra_dp_lt_config()
1056 	for (cnt = 0; cnt < n_lanes; cnt++) {  in tegra_dp_lt_config()
1057 		u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]);  in tegra_dp_lt_config()
1058 		u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]);  in tegra_dp_lt_config()
1060 		val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) |  in tegra_dp_lt_config()
1064 			(pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |  in tegra_dp_lt_config()
1068 		tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val);  in tegra_dp_lt_config()
1072 		for (cnt = 0; cnt < n_lanes / 2; cnt++) {  in tegra_dp_lt_config()
1073 			u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]);  in tegra_dp_lt_config()
1074 			u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]);  in tegra_dp_lt_config()
1075 			val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) |  in tegra_dp_lt_config()
1079 				(pc[cnt + 1] <<  in tegra_dp_lt_config()
1086 					       cnt, val);  in tegra_dp_lt_config()