304 	int ret = 0;  in tegra_dc_dpaux_read()  local
311 		ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,  in tegra_dc_dpaux_read()
313 		if (ret)  in tegra_dc_dpaux_read()
324 	return ret;  in tegra_dc_dpaux_read()
332 	int ret;  in tegra_dc_dp_dpcd_read()  local
334 	ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,  in tegra_dc_dp_dpcd_read()
336 	if (ret) {  in tegra_dc_dp_dpcd_read()
341 	return ret;  in tegra_dc_dp_dpcd_read()
349 	int ret;  in tegra_dc_dp_dpcd_write()  local
351 	ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,  in tegra_dc_dp_dpcd_write()
353 	if (ret) {  in tegra_dc_dp_dpcd_write()
358 	return ret;  in tegra_dc_dp_dpcd_write()
365 	int ret = 0;  in tegra_dc_i2c_aux_read()  local
371 		ret = tegra_dc_dpaux_write_chunk(  in tegra_dc_i2c_aux_read()
374 		if (ret) {  in tegra_dc_i2c_aux_read()
377 			return ret;  in tegra_dc_i2c_aux_read()
380 		ret = tegra_dc_dpaux_read_chunk(  in tegra_dc_i2c_aux_read()
383 		if (ret) {  in tegra_dc_i2c_aux_read()
385 			return ret;  in tegra_dc_i2c_aux_read()
663 	int ret;  in tegra_dc_dp_init_max_link_cfg()  local
665 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
666 	if (ret)  in tegra_dc_dp_init_max_link_cfg()
667 		return ret;  in tegra_dc_dp_init_max_link_cfg()
676 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
677 	if (ret)  in tegra_dc_dp_init_max_link_cfg()
678 		return ret;  in tegra_dc_dp_init_max_link_cfg()
682 	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL,  in tegra_dc_dp_init_max_link_cfg()
684 	if (ret)  in tegra_dc_dp_init_max_link_cfg()
685 		return ret;  in tegra_dc_dp_init_max_link_cfg()
686 	ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE,  in tegra_dc_dp_init_max_link_cfg()
688 	if (ret)  in tegra_dc_dp_init_max_link_cfg()
689 		return ret;  in tegra_dc_dp_init_max_link_cfg()
699 	ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data);  in tegra_dc_dp_init_max_link_cfg()
700 	if (ret)  in tegra_dc_dp_init_max_link_cfg()
701 		return ret;  in tegra_dc_dp_init_max_link_cfg()
722 	int ret;  in tegra_dc_dp_set_assr()  local
728 	ret = tegra_dc_dp_dpcd_write(priv, DP_EDP_CONFIGURATION_SET,  in tegra_dc_dp_set_assr()
730 	if (ret)  in tegra_dc_dp_set_assr()
731 		return ret;  in tegra_dc_dp_set_assr()
753 	int	ret;  in tegra_dp_set_lane_count()  local
759 	ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data);  in tegra_dp_set_lane_count()
760 	if (ret)  in tegra_dp_set_lane_count()
761 		return ret;  in tegra_dp_set_lane_count()
775 	int ret;  in tegra_dc_dp_link_trained()  local
778 		ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ?  in tegra_dc_dp_link_trained()
781 		if (ret)  in tegra_dc_dp_link_trained()
782 			return ret;  in tegra_dc_dp_link_trained()
803 	int ret;  in tegra_dp_channel_eq_status()  local
806 		ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data);  in tegra_dp_channel_eq_status()
807 		if (ret)  in tegra_dp_channel_eq_status()
808 			return ret;  in tegra_dp_channel_eq_status()
828 		ret = tegra_dc_dp_dpcd_read(dp,  in tegra_dp_channel_eq_status()
831 		if (ret)  in tegra_dp_channel_eq_status()
832 			return ret;  in tegra_dp_channel_eq_status()
846 	int ret;  in tegra_dp_clock_recovery_status()  local
849 		ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt),  in tegra_dp_clock_recovery_status()
851 		if (ret)  in tegra_dp_clock_recovery_status()
852 			return ret;  in tegra_dp_clock_recovery_status()
872 	int ret;  in tegra_dp_lt_adjust()  local
875 		ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt,  in tegra_dp_lt_adjust()
877 		if (ret)  in tegra_dp_lt_adjust()
878 			return ret;  in tegra_dp_lt_adjust()
891 		ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2,  in tegra_dp_lt_adjust()
893 		if (ret)  in tegra_dp_lt_adjust()
894 			return ret;  in tegra_dp_lt_adjust()
931 	int ret;  in tegra_dp_link_config()  local
939 	ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data);  in tegra_dp_link_config()
940 	if (ret)  in tegra_dp_link_config()
941 		return ret;  in tegra_dp_link_config()
948 			ret = tegra_dc_dp_dpcd_write(dp, DP_SET_POWER,  in tegra_dp_link_config()
950 			if (!ret)  in tegra_dp_link_config()
954 				return ret;  in tegra_dp_link_config()
961 		ret = tegra_dc_dp_set_assr(dp, dp->sor, 1);  in tegra_dp_link_config()
962 		if (ret)  in tegra_dp_link_config()
963 			return ret;  in tegra_dp_link_config()
966 	ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw);  in tegra_dp_link_config()
967 	if (ret) {  in tegra_dp_link_config()
969 		return ret;  in tegra_dp_link_config()
971 	ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor);  in tegra_dp_link_config()
972 	if (ret) {  in tegra_dp_link_config()
974 		return ret;  in tegra_dp_link_config()
987 	int ret;  in tegra_dp_lower_link_config()  local
992 	ret = _tegra_dp_lower_link_config(dp, cfg);  in tegra_dp_lower_link_config()
993 	if (!ret)  in tegra_dp_lower_link_config()
994 		ret = tegra_dc_dp_calc_config(dp, timing, cfg);  in tegra_dp_lower_link_config()
995 	if (!ret)  in tegra_dp_lower_link_config()
996 		ret = tegra_dp_link_config(dp, cfg);  in tegra_dp_lower_link_config()
997 	if (ret)  in tegra_dp_lower_link_config()
1005 	return ret;  in tegra_dp_lower_link_config()
1101 		int ret;  in _tegra_dp_channel_eq()  local
1104 			ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported,  in _tegra_dp_channel_eq()
1106 			if (ret)  in _tegra_dp_channel_eq()
1107 				return ret;  in _tegra_dp_channel_eq()
1131 	int ret;  in tegra_dp_channel_eq()  local
1139 	ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg);  in tegra_dp_channel_eq()
1143 	return ret;  in tegra_dp_channel_eq()
1314 	int	ret;  in tegra_dp_do_link_training()  local
1317 		ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor);  in tegra_dp_do_link_training()
1318 		if (ret) {  in tegra_dp_do_link_training()
1325 			ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg);  in tegra_dp_do_link_training()
1326 			if (ret)  in tegra_dp_do_link_training()
1330 		ret = -ENOSYS;  in tegra_dp_do_link_training()
1332 	if (ret) {  in tegra_dp_do_link_training()
1334 		ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg);  in tegra_dp_do_link_training()
1335 		if (ret) {  in tegra_dp_do_link_training()
1337 			return ret;  in tegra_dp_do_link_training()
1408 	int ret;  in tegra_dc_dp_sink_out_of_sync()  local
1412 	ret = tegra_dc_dp_dpcd_read(dp, DP_SINK_STATUS, &dpcd_data);  in tegra_dc_dp_sink_out_of_sync()
1413 	if (ret)  in tegra_dc_dp_sink_out_of_sync()
1414 		return ret;  in tegra_dc_dp_sink_out_of_sync()
1442 		int ret;  in tegra_dc_dp_check_sink()  local
1453 		ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor);  in tegra_dc_dp_check_sink()
1454 		if (ret)  in tegra_dc_dp_check_sink()
1455 			return ret;  in tegra_dc_dp_check_sink()
1479 	int ret;  in tegra_dp_enable()  local
1498 	ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor);  in tegra_dp_enable()
1499 	if (ret || !sor) {  in tegra_dp_enable()
1500 		debug("dp: failed to find SOR device: ret=%d\n", ret);  in tegra_dp_enable()
1501 		return ret;  in tegra_dp_enable()
1504 	ret = tegra_dc_sor_enable_dp(sor, link_cfg);  in tegra_dp_enable()
1505 	if (ret)  in tegra_dp_enable()
1506 		return ret;  in tegra_dp_enable()
1514 		ret = tegra_dc_dp_dpcd_write(priv, DP_SET_POWER, data);  in tegra_dp_enable()
1515 	} while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret);  in tegra_dp_enable()
1517 	if (ret || retry >= DP_POWER_ON_MAX_TRIES) {  in tegra_dp_enable()
1518 		debug("dp: failed to power on panel (0x%x)\n", ret);  in tegra_dp_enable()
1542 	ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);  in tegra_dp_enable()
1543 	if (ret && ret != -EEXIST)  in tegra_dp_enable()
1544 		return ret;  in tegra_dp_enable()
1551 		ret = tegra_dc_dp_check_sink(priv, link_cfg, timing);  in tegra_dp_enable()
1552 		if (ret)  in tegra_dp_enable()
1553 			return ret;  in tegra_dp_enable()
1559 	ret = video_bridge_set_backlight(sor, 80);  in tegra_dp_enable()
1560 	if (ret) {  in tegra_dp_enable()
1562 		return ret;  in tegra_dp_enable()