55 static int update_display_mode(struct dc_ctlr *disp_ctrl,  in update_display_mode()  argument
61 	writel(0x1, &disp_ctrl->disp.disp_timing_opt);  in update_display_mode()
64 	       &disp_ctrl->disp.ref_to_sync);  in update_display_mode()
67 	       &disp_ctrl->disp.sync_width);  in update_display_mode()
70 		timing->hback_porch.typ, &disp_ctrl->disp.back_porch);  in update_display_mode()
73 		timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);  in update_display_mode()
76 	       &disp_ctrl->disp.disp_active);  in update_display_mode()
93 	       &disp_ctrl->disp.disp_clk_ctrl);  in update_display_mode()
120 int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)  in tegra_dc_sor_general_act()  argument
122 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_general_act()
124 	if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,  in tegra_dc_sor_general_act()
146 void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,  in tegra_dc_sor_disable_win_short_raster()  argument
152 	selected_windows = readl(&disp_ctrl->cmd.disp_win_header);  in tegra_dc_sor_disable_win_short_raster()
156 		writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);  in tegra_dc_sor_disable_win_short_raster()
157 		dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);  in tegra_dc_sor_disable_win_short_raster()
158 		writel(0, &disp_ctrl->win.win_opt);  in tegra_dc_sor_disable_win_short_raster()
159 		writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_disable_win_short_raster()
162 	writel(selected_windows, &disp_ctrl->cmd.disp_win_header);  in tegra_dc_sor_disable_win_short_raster()
165 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);  in tegra_dc_sor_disable_win_short_raster()
167 	       &disp_ctrl->disp.ref_to_sync);  in tegra_dc_sor_disable_win_short_raster()
169 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);  in tegra_dc_sor_disable_win_short_raster()
171 	       &disp_ctrl->disp.sync_width);  in tegra_dc_sor_disable_win_short_raster()
173 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);  in tegra_dc_sor_disable_win_short_raster()
175 	       &disp_ctrl->disp.back_porch);  in tegra_dc_sor_disable_win_short_raster()
177 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);  in tegra_dc_sor_disable_win_short_raster()
179 	       &disp_ctrl->disp.front_porch);  in tegra_dc_sor_disable_win_short_raster()
181 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);  in tegra_dc_sor_disable_win_short_raster()
183 	       &disp_ctrl->disp.disp_active);  in tegra_dc_sor_disable_win_short_raster()
185 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_disable_win_short_raster()
189 void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,  in tegra_dc_sor_restore_win_and_raster()  argument
194 	selected_windows = readl(&disp_ctrl->cmd.disp_win_header);  in tegra_dc_sor_restore_win_and_raster()
197 		writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);  in tegra_dc_sor_restore_win_and_raster()
198 		writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);  in tegra_dc_sor_restore_win_and_raster()
199 		writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_restore_win_and_raster()
202 	writel(selected_windows, &disp_ctrl->cmd.disp_win_header);  in tegra_dc_sor_restore_win_and_raster()
204 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);  in tegra_dc_sor_restore_win_and_raster()
205 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);  in tegra_dc_sor_restore_win_and_raster()
206 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);  in tegra_dc_sor_restore_win_and_raster()
207 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);  in tegra_dc_sor_restore_win_and_raster()
208 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);  in tegra_dc_sor_restore_win_and_raster()
210 	writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_restore_win_and_raster()
226 static int update_window(struct dc_ctlr *disp_ctrl,  in update_window()  argument
234 	writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);  in update_window()
237 	       &disp_ctrl->win.size);  in update_window()
240 		&disp_ctrl->win.prescaled_size);  in update_window()
242 		32 * 32), &disp_ctrl->win.line_stride);  in update_window()
248 	writel(colour_depth, &disp_ctrl->win.color_depth);  in update_window()
250 	writel(frame_buffer, &disp_ctrl->winbuf.start_addr);  in update_window()
252 	       &disp_ctrl->win.dda_increment);  in update_window()
254 	writel(colour_white, &disp_ctrl->disp.blend_background_color);  in update_window()
256 	       &disp_ctrl->cmd.disp_cmd);  in update_window()
258 	writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in update_window()
262 	writel(val, &disp_ctrl->cmd.state_ctrl);  in update_window()
265 	val = readl(&disp_ctrl->win.win_opt);  in update_window()
266 	writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);  in update_window()
271 static int tegra_dc_init(struct dc_ctlr *disp_ctrl)  in tegra_dc_init()  argument
274 	writel(0x00000000, &disp_ctrl->cmd.int_mask);  in tegra_dc_init()
276 	       &disp_ctrl->cmd.state_access);  in tegra_dc_init()
277 	writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);  in tegra_dc_init()
278 	writel(0x00000000, &disp_ctrl->win.win_opt);  in tegra_dc_init()
279 	writel(0x00000000, &disp_ctrl->win.byte_swap);  in tegra_dc_init()
280 	writel(0x00000000, &disp_ctrl->win.buffer_ctrl);  in tegra_dc_init()
282 	writel(0x00000000, &disp_ctrl->win.pos);  in tegra_dc_init()
283 	writel(0x00000000, &disp_ctrl->win.h_initial_dda);  in tegra_dc_init()
284 	writel(0x00000000, &disp_ctrl->win.v_initial_dda);  in tegra_dc_init()
285 	writel(0x00000000, &disp_ctrl->win.dda_increment);  in tegra_dc_init()
286 	writel(0x00000000, &disp_ctrl->win.dv_ctrl);  in tegra_dc_init()
288 	writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);  in tegra_dc_init()
289 	writel(0x00000000, &disp_ctrl->win.blend_match_select);  in tegra_dc_init()
290 	writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);  in tegra_dc_init()
291 	writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);  in tegra_dc_init()
293 	writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);  in tegra_dc_init()
294 	writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);  in tegra_dc_init()
295 	writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);  in tegra_dc_init()
297 	writel(0x00000000, &disp_ctrl->com.crc_checksum);  in tegra_dc_init()
298 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);  in tegra_dc_init()
299 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);  in tegra_dc_init()
300 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);  in tegra_dc_init()
301 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);  in tegra_dc_init()
302 	writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);  in tegra_dc_init()