69 	setbits_le32(&phy->ctrl, BIT(0));  in sunxi_dw_hdmi_phy_init()
71 	setbits_le32(&phy->ctrl, BIT(16));  in sunxi_dw_hdmi_phy_init()
72 	setbits_le32(&phy->ctrl, BIT(1));  in sunxi_dw_hdmi_phy_init()
74 	setbits_le32(&phy->ctrl, BIT(2));  in sunxi_dw_hdmi_phy_init()
76 	setbits_le32(&phy->ctrl, BIT(3));  in sunxi_dw_hdmi_phy_init()
78 	setbits_le32(&phy->ctrl, BIT(19));  in sunxi_dw_hdmi_phy_init()
80 	setbits_le32(&phy->ctrl, BIT(18));  in sunxi_dw_hdmi_phy_init()
81 	setbits_le32(&phy->ctrl, 7 << 4);  in sunxi_dw_hdmi_phy_init()
92 	setbits_le32(&phy->ctrl, 0xf << 8);  in sunxi_dw_hdmi_phy_init()
93 	setbits_le32(&phy->ctrl, BIT(7));  in sunxi_dw_hdmi_phy_init()
99 	setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_init()
102 	setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_init()
103 	setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_init()
153 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
156 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
158 			setbits_le32(&phy->pll, tmp + 2);  in sunxi_dw_hdmi_phy_set()
160 			setbits_le32(&phy->pll, 0x3f);  in sunxi_dw_hdmi_phy_set()
171 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
174 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
175 		setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_set()
185 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
188 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
189 		setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_set()
199 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
202 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
203 		setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_set()
255 		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);  in sunxi_dw_hdmi_lcdc_init()
258 		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);  in sunxi_dw_hdmi_lcdc_init()
265 		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);  in sunxi_dw_hdmi_lcdc_init()
268 		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);  in sunxi_dw_hdmi_lcdc_init()
314 		setbits_le32(&phy->pol, 0x300);  in sunxi_dw_hdmi_enable()
317 	setbits_le32(&phy->ctrl, 0xf << 12);  in sunxi_dw_hdmi_enable()
346 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);  in sunxi_dw_hdmi_probe()
347 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);  in sunxi_dw_hdmi_probe()
348 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);  in sunxi_dw_hdmi_probe()
349 	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);  in sunxi_dw_hdmi_probe()
352 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);  in sunxi_dw_hdmi_probe()