58 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,  in sunxi_de2_mode_set()  argument
61 	ulong de_mux_base = (mux == 0) ?  in sunxi_de2_mode_set()
84 	setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);  in sunxi_de2_mode_set()
86 	setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));  in sunxi_de2_mode_set()
88 	setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));  in sunxi_de2_mode_set()
89 	setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));  in sunxi_de2_mode_set()
179 			  struct udevice *disp, int mux, bool is_composite)  in sunxi_de2_init()  argument
193 	disp_uc_plat->source_id = mux;  in sunxi_de2_init()
209 	sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);  in sunxi_de2_init()
238 		int mux;  in sunxi_de2_probe()  local
240 			mux = 0;  in sunxi_de2_probe()
242 			mux = 1;  in sunxi_de2_probe()
244 		ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,  in sunxi_de2_probe()