Lines Matching refs:regs
53 static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) in rk_mipi_dsi_write() argument
59 uintptr_t addr = (reg >> ADDR_SHIFT) + regs; in rk_mipi_dsi_write()
85 uintptr_t regs = priv->regs; in rk_mipi_dsi_enable() local
92 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
93 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); in rk_mipi_dsi_enable()
94 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
97 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
98 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); in rk_mipi_dsi_enable()
99 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); in rk_mipi_dsi_enable()
100 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); in rk_mipi_dsi_enable()
104 rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val); in rk_mipi_dsi_enable()
107 rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val); in rk_mipi_dsi_enable()
110 rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val); in rk_mipi_dsi_enable()
113 rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val); in rk_mipi_dsi_enable()
116 rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE); in rk_mipi_dsi_enable()
119 rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE); in rk_mipi_dsi_enable()
122 rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0); in rk_mipi_dsi_enable()
131 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1); in rk_mipi_dsi_enable()
134 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); in rk_mipi_dsi_enable()
137 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT); in rk_mipi_dsi_enable()
140 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); in rk_mipi_dsi_enable()
143 rk_mipi_dsi_write(regs, LP_CMD_EN, 1); in rk_mipi_dsi_enable()
144 rk_mipi_dsi_write(regs, LP_HFP_EN, 1); in rk_mipi_dsi_enable()
145 rk_mipi_dsi_write(regs, LP_VACT_EN, 1); in rk_mipi_dsi_enable()
146 rk_mipi_dsi_write(regs, LP_VFP_EN, 1); in rk_mipi_dsi_enable()
147 rk_mipi_dsi_write(regs, LP_VBP_EN, 1); in rk_mipi_dsi_enable()
148 rk_mipi_dsi_write(regs, LP_VSA_EN, 1); in rk_mipi_dsi_enable()
151 rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a); in rk_mipi_dsi_enable()
154 rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk); in rk_mipi_dsi_enable()
157 rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8); in rk_mipi_dsi_enable()
160 rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32); in rk_mipi_dsi_enable()
161 rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1); in rk_mipi_dsi_enable()
162 rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14); in rk_mipi_dsi_enable()
163 rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10); in rk_mipi_dsi_enable()
164 rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710); in rk_mipi_dsi_enable()
167 rk_mipi_dsi_write(regs, SHUTDOWNZ, 1); in rk_mipi_dsi_enable()
173 static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code, in rk_mipi_phy_write() argument
179 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); in rk_mipi_phy_write()
180 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code); in rk_mipi_phy_write()
181 rk_mipi_dsi_write(regs, PHY_TESTEN, 1); in rk_mipi_phy_write()
182 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); in rk_mipi_phy_write()
183 rk_mipi_dsi_write(regs, PHY_TESTEN, 0); in rk_mipi_phy_write()
187 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); in rk_mipi_phy_write()
188 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]); in rk_mipi_phy_write()
189 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); in rk_mipi_phy_write()
202 uintptr_t regs = priv->regs; in rk_mipi_phy_enable() local
226 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0); in rk_mipi_phy_enable()
227 rk_mipi_dsi_write(regs, PHY_RSTZ, 0); in rk_mipi_phy_enable()
228 rk_mipi_dsi_write(regs, PHY_TESTCLR, 1); in rk_mipi_phy_enable()
231 rk_mipi_dsi_write(regs, PHY_TESTCLR, 0); in rk_mipi_phy_enable()
235 rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1); in rk_mipi_phy_enable()
238 rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1); in rk_mipi_phy_enable()
241 rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1); in rk_mipi_phy_enable()
253 rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1); in rk_mipi_phy_enable()
290 rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1); in rk_mipi_phy_enable()
292 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); in rk_mipi_phy_enable()
294 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); in rk_mipi_phy_enable()
296 rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1); in rk_mipi_phy_enable()
300 rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1); in rk_mipi_phy_enable()
303 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); in rk_mipi_phy_enable()
306 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); in rk_mipi_phy_enable()
309 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); in rk_mipi_phy_enable()
312 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); in rk_mipi_phy_enable()
315 rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME, in rk_mipi_phy_enable()
318 rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME, in rk_mipi_phy_enable()
321 rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME, in rk_mipi_phy_enable()
325 rk_mipi_dsi_write(regs, N_LANES, 0x03); in rk_mipi_phy_enable()
326 rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1); in rk_mipi_phy_enable()
327 rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1); in rk_mipi_phy_enable()
328 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1); in rk_mipi_phy_enable()
329 rk_mipi_dsi_write(regs, PHY_RSTZ, 1); in rk_mipi_phy_enable()