40 	struct rk3288_edp *regs;  member
47 static void rk_edp_init_refclk(struct rk3288_edp *regs)  in rk_edp_init_refclk()  argument
49 	writel(SEL_24M, &regs->analog_ctl_2);  in rk_edp_init_refclk()
50 	writel(REF_CLK_24M, &regs->pll_reg_1);  in rk_edp_init_refclk()
53 	       V2L_CUR_SEL_1MA, &regs->pll_reg_2);  in rk_edp_init_refclk()
57 	       &regs->pll_reg_3);  in rk_edp_init_refclk()
61 	       &regs->pll_reg_5);  in rk_edp_init_refclk()
63 	writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &regs->ssc_reg);  in rk_edp_init_refclk()
67 	       &regs->tx_common);  in rk_edp_init_refclk()
70 	       &regs->dp_aux);  in rk_edp_init_refclk()
73 	       &regs->dp_bias);  in rk_edp_init_refclk()
76 	       &regs->dp_reserv2);  in rk_edp_init_refclk()
79 static void rk_edp_init_interrupt(struct rk3288_edp *regs)  in rk_edp_init_interrupt()  argument
82 	writel(INT_POL, &regs->int_ctl);  in rk_edp_init_interrupt()
85 	writel(0xff, &regs->common_int_sta_1);  in rk_edp_init_interrupt()
86 	writel(0x4f, &regs->common_int_sta_2);  in rk_edp_init_interrupt()
87 	writel(0xff, &regs->common_int_sta_3);  in rk_edp_init_interrupt()
88 	writel(0x27, &regs->common_int_sta_4);  in rk_edp_init_interrupt()
89 	writel(0x7f, &regs->dp_int_sta);  in rk_edp_init_interrupt()
92 	writel(0x00, &regs->common_int_mask_1);  in rk_edp_init_interrupt()
93 	writel(0x00, &regs->common_int_mask_2);  in rk_edp_init_interrupt()
94 	writel(0x00, &regs->common_int_mask_3);  in rk_edp_init_interrupt()
95 	writel(0x00, &regs->common_int_mask_4);  in rk_edp_init_interrupt()
96 	writel(0x00, &regs->int_sta_mask);  in rk_edp_init_interrupt()
99 static void rk_edp_enable_sw_function(struct rk3288_edp *regs)  in rk_edp_enable_sw_function()  argument
101 	clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);  in rk_edp_enable_sw_function()
104 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)  in rk_edp_get_pll_locked()  argument
108 	val = readl(&regs->dp_debug_ctl);  in rk_edp_get_pll_locked()
113 static int rk_edp_init_analog_func(struct rk3288_edp *regs)  in rk_edp_init_analog_func()  argument
117 	writel(0x00, &regs->dp_pd);  in rk_edp_init_analog_func()
118 	writel(PLL_LOCK_CHG, &regs->common_int_sta_1);  in rk_edp_init_analog_func()
120 	clrbits_le32(&regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);  in rk_edp_init_analog_func()
123 	while (!rk_edp_get_pll_locked(regs)) {  in rk_edp_init_analog_func()
131 	clrbits_le32(&regs->func_en_2, SERDES_FIFO_FUNC_EN_N |  in rk_edp_init_analog_func()
138 static void rk_edp_init_aux(struct rk3288_edp *regs)  in rk_edp_init_aux()  argument
141 	writel(AUX_FUNC_EN_N, &regs->dp_int_sta);  in rk_edp_init_aux()
144 	setbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);  in rk_edp_init_aux()
147 	writel(DEFER_CTRL_EN | DEFER_COUNT(1), &regs->aux_ch_defer_dtl);  in rk_edp_init_aux()
150 	clrbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);  in rk_edp_init_aux()
153 static int rk_edp_aux_enable(struct rk3288_edp *regs)  in rk_edp_aux_enable()  argument
157 	setbits_le32(&regs->aux_ch_ctl_2, AUX_EN);  in rk_edp_aux_enable()
160 		if (!(readl(&regs->aux_ch_ctl_2) & AUX_EN))  in rk_edp_aux_enable()
167 static int rk_edp_is_aux_reply(struct rk3288_edp *regs)  in rk_edp_is_aux_reply()  argument
172 	while (!(readl(&regs->dp_int_sta) & RPLY_RECEIV)) {  in rk_edp_is_aux_reply()
177 	writel(RPLY_RECEIV, &regs->dp_int_sta);  in rk_edp_is_aux_reply()
182 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)  in rk_edp_start_aux_transaction()  argument
187 	ret = rk_edp_aux_enable(regs);  in rk_edp_start_aux_transaction()
194 	if (rk_edp_is_aux_reply(regs)) {  in rk_edp_start_aux_transaction()
200 	val = readl(&regs->dp_int_sta);  in rk_edp_start_aux_transaction()
202 		writel(AUX_ERR, &regs->dp_int_sta);  in rk_edp_start_aux_transaction()
207 	val = readl(&regs->dp_int_sta);  in rk_edp_start_aux_transaction()
216 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,  in rk_edp_dpcd_transfer()  argument
232 			writel(BUF_CLR, &regs->buf_data_ctl);  in rk_edp_dpcd_transfer()
235 			writel(AUX_ADDR_7_0(val_addr), &regs->aux_addr_7_0);  in rk_edp_dpcd_transfer()
236 			writel(AUX_ADDR_15_8(val_addr), &regs->aux_addr_15_8);  in rk_edp_dpcd_transfer()
237 			writel(AUX_ADDR_19_16(val_addr), &regs->aux_addr_19_16);  in rk_edp_dpcd_transfer()
249 					writel(*data++, &regs->buf_data[i]);  in rk_edp_dpcd_transfer()
255 			writel(val, &regs->aux_ch_ctl_1);  in rk_edp_dpcd_transfer()
258 			ret = rk_edp_start_aux_transaction(regs);  in rk_edp_dpcd_transfer()
270 				*data++ = (u8)readl(&regs->buf_data[i]);  in rk_edp_dpcd_transfer()
281 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,  in rk_edp_dpcd_read()  argument
284 	return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);  in rk_edp_dpcd_read()
287 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,  in rk_edp_dpcd_write()  argument
290 	return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);  in rk_edp_dpcd_write()
303 	ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);  in rk_edp_link_power_up()
310 	ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);  in rk_edp_link_power_up()
331 	return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,  in rk_edp_link_configure()
341 		writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);  in rk_edp_set_link_training()
352 	return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,  in rk_edp_dpcd_read_link_status()
464 	struct rk3288_edp *regs = edp->regs;  in rk_edp_link_train_cr()  local
472 	writel(value, &regs->dp_training_ptn_set);  in rk_edp_link_train_cr()
473 	ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);  in rk_edp_link_train_cr()
485 		ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,  in rk_edp_link_train_cr()
544 	struct rk3288_edp *regs = edp->regs;  in rk_edp_link_train_ce()  local
552 	writel(value, &regs->dp_training_ptn_set);  in rk_edp_link_train_ce()
553 	ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);  in rk_edp_link_train_ce()
594 	ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,  in rk_edp_init_training()
635 	writel(edp->link_train.link_rate, &edp->regs->link_bw_set);  in rk_edp_hw_link_training()
636 	writel(edp->link_train.lane_count, &edp->regs->lane_count_set);  in rk_edp_hw_link_training()
645 	writel(HW_LT_EN, &edp->regs->dp_hw_link_training);  in rk_edp_hw_link_training()
648 		val = readl(&edp->regs->dp_hw_link_training);  in rk_edp_hw_link_training()
662 static int rk_edp_select_i2c_device(struct rk3288_edp *regs,  in rk_edp_select_i2c_device()  argument
669 	writel(device_addr, &regs->aux_addr_7_0);  in rk_edp_select_i2c_device()
670 	writel(0x0, &regs->aux_addr_15_8);  in rk_edp_select_i2c_device()
671 	writel(0x0, &regs->aux_addr_19_16);  in rk_edp_select_i2c_device()
674 	writel(val_addr, &regs->buf_data[0]);  in rk_edp_select_i2c_device()
682 	       AUX_TX_COMM_WRITE, &regs->aux_ch_ctl_1);  in rk_edp_select_i2c_device()
685 	ret = rk_edp_start_aux_transaction(regs);  in rk_edp_select_i2c_device()
694 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,  in rk_edp_i2c_read()  argument
706 			writel(BUF_CLR, &regs->buf_data_ctl);  in rk_edp_i2c_read()
709 			clrbits_le32(&regs->aux_ch_ctl_2, ADDR_ONLY);  in rk_edp_i2c_read()
716 				ret = rk_edp_select_i2c_device(regs,  in rk_edp_i2c_read()
729 			       AUX_TX_COMM_READ, &regs->aux_ch_ctl_1);  in rk_edp_i2c_read()
732 			ret = rk_edp_start_aux_transaction(regs);  in rk_edp_i2c_read()
741 			val = readl(&regs->aux_rx_comm);  in rk_edp_i2c_read()
753 			val = readl(&regs->buf_data[cur_data_idx]);  in rk_edp_i2c_read()
778 static void rk_edp_init_video(struct rk3288_edp *regs)  in rk_edp_init_video()  argument
781 	       &regs->common_int_sta_1);  in rk_edp_init_video()
782 	writel(CHA_CRI(4) | CHA_CTRL, &regs->sys_ctl_2);  in rk_edp_init_video()
783 	writel(VID_HRES_TH(2) | VID_VRES_TH(0), &regs->video_ctl_8);  in rk_edp_init_video()
786 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)  in rk_edp_config_video_slave_mode()  argument
788 	clrbits_le32(&regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);  in rk_edp_config_video_slave_mode()
791 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,  in rk_edp_set_video_cr_mn()  argument
797 		setbits_le32(&regs->sys_ctl_4, FIX_M_VID);  in rk_edp_set_video_cr_mn()
798 		writel(m_value & 0xff, &regs->m_vid_0);  in rk_edp_set_video_cr_mn()
799 		writel((m_value >> 8) & 0xff, &regs->m_vid_1);  in rk_edp_set_video_cr_mn()
800 		writel((m_value >> 16) & 0xff, &regs->m_vid_2);  in rk_edp_set_video_cr_mn()
802 		writel(n_value & 0xf, &regs->n_vid_0);  in rk_edp_set_video_cr_mn()
803 		writel((n_value >> 8) & 0xff, &regs->n_vid_1);  in rk_edp_set_video_cr_mn()
804 		writel((n_value >> 16) & 0xff, &regs->n_vid_2);  in rk_edp_set_video_cr_mn()
806 		clrbits_le32(&regs->sys_ctl_4, FIX_M_VID);  in rk_edp_set_video_cr_mn()
808 		writel(0x00, &regs->n_vid_0);  in rk_edp_set_video_cr_mn()
809 		writel(0x80, &regs->n_vid_1);  in rk_edp_set_video_cr_mn()
810 		writel(0x00, &regs->n_vid_2);  in rk_edp_set_video_cr_mn()
814 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)  in rk_edp_is_video_stream_clock_on()  argument
821 		val = readl(&regs->sys_ctl_1);  in rk_edp_is_video_stream_clock_on()
824 		writel(val, &regs->sys_ctl_1);  in rk_edp_is_video_stream_clock_on()
825 		val = readl(&regs->sys_ctl_1);  in rk_edp_is_video_stream_clock_on()
829 		val = readl(&regs->sys_ctl_2);  in rk_edp_is_video_stream_clock_on()
832 		writel(val, &regs->sys_ctl_2);  in rk_edp_is_video_stream_clock_on()
833 		val = readl(&regs->sys_ctl_2);  in rk_edp_is_video_stream_clock_on()
849 		val = readl(&edp->regs->sys_ctl_3);  in rk_edp_is_video_stream_on()
852 		writel(val, &edp->regs->sys_ctl_3);  in rk_edp_is_video_stream_on()
854 		val = readl(&edp->regs->sys_ctl_3);  in rk_edp_is_video_stream_on()
866 	rk_edp_config_video_slave_mode(edp->regs);  in rk_edp_config_video()
868 	if (!rk_edp_get_pll_locked(edp->regs)) {  in rk_edp_config_video()
873 	ret = rk_edp_is_video_stream_clock_on(edp->regs);  in rk_edp_config_video()
878 	rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);  in rk_edp_config_video()
881 	clrbits_le32(&edp->regs->video_ctl_10, F_SEL);  in rk_edp_config_video()
884 	clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);  in rk_edp_config_video()
887 	setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);  in rk_edp_config_video()
894 	setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);  in rockchip_edp_force_hpd()
901 	val = readl(&edp->regs->sys_ctl_3);  in rockchip_edp_get_plug_in_status()
943 	rk_edp_init_video(priv->regs);  in rk_edp_enable()
966 		ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,  in rk_edp_read_edid()
979 			ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,  in rk_edp_read_edid()
1001 	priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);  in rk_edp_ofdata_to_platdata()
1010 	struct rk3288_edp *regs = priv->regs;  in rk_edp_remove()  local
1012 	setbits_le32(&regs->video_ctl_1, VIDEO_MUTE);  in rk_edp_remove()
1013 	clrbits_le32(&regs->video_ctl_1, VIDEO_EN);  in rk_edp_remove()
1014 	clrbits_le32(&regs->sys_ctl_3, F_HPD | HPD_CTRL);  in rk_edp_remove()
1015 	setbits_le32(&regs->func_en_1, SW_FUNC_EN_N);  in rk_edp_remove()
1024 	struct rk3288_edp *regs = priv->regs;  in rk_edp_probe()  local
1068 	rk_edp_init_refclk(regs);  in rk_edp_probe()
1069 	rk_edp_init_interrupt(regs);  in rk_edp_probe()
1070 	rk_edp_enable_sw_function(regs);  in rk_edp_probe()
1071 	ret = rk_edp_init_analog_func(regs);  in rk_edp_probe()
1074 	rk_edp_init_aux(regs);  in rk_edp_probe()