264 static inline void regs_dump(struct ebc_tcon_priv *tcon)  in regs_dump()  argument
271 			printf("\n 0x%p:\t", tcon->reg + i);  in regs_dump()
272 		printf("0x%x\t", readl(tcon->reg + i));  in regs_dump()
277 			printf("\n 0x%p:\t", tcon->reg + i);  in regs_dump()
278 		printf("0x%x\t", readl(tcon->reg + i));  in regs_dump()
313 static inline void tcon_write(struct ebc_tcon_priv *tcon, unsigned int reg,  in tcon_write()  argument
316 	unsigned int *cache = tcon->regcache + (reg >> 2);  in tcon_write()
318 	writel(value, tcon->reg + reg);  in tcon_write()
322 static inline unsigned int tcon_read(struct ebc_tcon_priv *tcon,  in tcon_read()  argument
325 	return readl(tcon->reg + reg);  in tcon_read()
328 static inline void tcon_update_bits(struct ebc_tcon_priv *tcon,  in tcon_update_bits()  argument
333 	unsigned int *cache = tcon->regcache + (reg >> 2);  in tcon_update_bits()
338 	writel(tmp, tcon->reg + reg);  in tcon_update_bits()
347 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in ebc_irq_handler()  local
349 	intr_status = readl(tcon->reg + EBC_INT_STATUS);  in ebc_irq_handler()
352 		tcon_update_bits(tcon, EBC_INT_STATUS,  in ebc_irq_handler()
359 static inline void tcon_cfg_done(struct ebc_tcon_priv *tcon)  in tcon_cfg_done()  argument
361 	writel(REG_LOAD_GLOBAL_EN, tcon->reg + EBC_CONFIG_DONE);  in tcon_cfg_done()
368 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in ebc_tcon_enable()  local
384 	tcon_write(tcon, EBC_DSP_HTIMING0,  in ebc_tcon_enable()
387 	tcon_write(tcon, EBC_DSP_HTIMING1,  in ebc_tcon_enable()
390 	tcon_write(tcon, EBC_DSP_VTIMING0,  in ebc_tcon_enable()
393 	tcon_write(tcon, EBC_DSP_VTIMING1,  in ebc_tcon_enable()
396 	tcon_write(tcon, EBC_DSP_ACT_INFO,  in ebc_tcon_enable()
399 	tcon_write(tcon, EBC_WIN_VIR,  in ebc_tcon_enable()
402 	tcon_write(tcon, EBC_WIN_ACT,  in ebc_tcon_enable()
405 	tcon_write(tcon, EBC_WIN_DSP,  in ebc_tcon_enable()
408 	tcon_write(tcon, EBC_WIN_DSP_ST,  in ebc_tcon_enable()
416 	tcon_write(tcon, EBC_WIN_CTRL,  in ebc_tcon_enable()
434 	tcon_write(tcon, EBC_EPD_CTRL,  in ebc_tcon_enable()
443 	tcon_write(tcon, EBC_DSP_START,  in ebc_tcon_enable()
446 	tcon_write(tcon, EBC_DSP_CTRL,  in ebc_tcon_enable()
451 	tcon_cfg_done(tcon);  in ebc_tcon_enable()
453 	ret = clk_set_rate(&tcon->dclk, panel->sdck * ((panel->panel_16bit ? 7 : 3) + 1));  in ebc_tcon_enable()
473 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in ebc_tcon_dsp_mode_set()  local
475 	tcon_update_bits(tcon, EBC_DSP_CTRL,  in ebc_tcon_dsp_mode_set()
480 	tcon_update_bits(tcon, EBC_EPD_CTRL, THREE_WIN_MODE_MASK,  in ebc_tcon_dsp_mode_set()
483 	tcon_update_bits(tcon, EBC_DSP_START,  in ebc_tcon_dsp_mode_set()
486 	tcon_cfg_done(tcon);  in ebc_tcon_dsp_mode_set()
495 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in ebc_tcon_image_addr_set()  local
497 	tcon_write(tcon, EBC_WIN_MST0, pre_image_addr);  in ebc_tcon_image_addr_set()
498 	tcon_write(tcon, EBC_WIN_MST1, cur_image_addr);  in ebc_tcon_image_addr_set()
499 	tcon_cfg_done(tcon);  in ebc_tcon_image_addr_set()
506 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in ebc_tcon_frame_addr_set()  local
508 	tcon_write(tcon, EBC_WIN_MST2, frame_addr);  in ebc_tcon_frame_addr_set()
509 	tcon_cfg_done(tcon);  in ebc_tcon_frame_addr_set()
518 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in ebc_tcon_lut_data_set()  local
521 		dev_err(tcon->dev, "frame count over flow\n");  in ebc_tcon_lut_data_set()
531 		tcon_write(tcon, EBC_LUT_DATA_ADDR + (i * 4), lut_data[i]);  in ebc_tcon_lut_data_set()
533 	tcon_cfg_done(tcon);  in ebc_tcon_lut_data_set()
543 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in wait_for_last_frame_complete()  local
557 		intr_status = readl(tcon->reg + EBC_INT_STATUS);  in wait_for_last_frame_complete()
563 	tcon_update_bits(tcon, EBC_INT_STATUS,  in wait_for_last_frame_complete()
572 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in ebc_tcon_frame_start()  local
574 	tcon_write(tcon, EBC_INT_STATUS,  in ebc_tcon_frame_start()
576 	tcon_update_bits(tcon, EBC_DSP_START,  in ebc_tcon_frame_start()
578 	tcon_cfg_done(tcon);  in ebc_tcon_frame_start()
580 	tcon_update_bits(tcon, EBC_DSP_START,  in ebc_tcon_frame_start()
590 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in rk3576_ebc_tcon_enable()  local
608 	tcon_write(tcon, RK3576_EBC_DSP_HTIMING0,  in rk3576_ebc_tcon_enable()
611 	tcon_write(tcon, RK3576_EBC_DSP_HTIMING1,  in rk3576_ebc_tcon_enable()
614 	tcon_write(tcon, RK3576_EBC_DSP_VTIMING0,  in rk3576_ebc_tcon_enable()
617 	tcon_write(tcon, RK3576_EBC_DSP_VTIMING1,  in rk3576_ebc_tcon_enable()
620 	tcon_write(tcon, RK3576_EBC_DSP_ACT_INFO,  in rk3576_ebc_tcon_enable()
623 	tcon_write(tcon, RK3576_EBC_WIN_VIR,  in rk3576_ebc_tcon_enable()
626 	tcon_write(tcon, RK3576_EBC_WIN_ACT,  in rk3576_ebc_tcon_enable()
629 	tcon_write(tcon, RK3576_EBC_WIN_DSP,  in rk3576_ebc_tcon_enable()
637 			dev_warn(tcon->dev,  in rk3576_ebc_tcon_enable()
653 		tcon_write(tcon, RK3576_EBC_WIN_DSP_ST, val);  in rk3576_ebc_tcon_enable()
655 		tcon_write(tcon, RK3576_EBC_WIN_DSP_ST,  in rk3576_ebc_tcon_enable()
666 	tcon_write(tcon, RK3576_EBC_WIN_CTRL,  in rk3576_ebc_tcon_enable()
673 	tcon_write(tcon, RK3576_EBC_WIN0_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) |  in rk3576_ebc_tcon_enable()
676 	tcon_write(tcon, RK3576_EBC_WIN1_CTRL, RK3576_WIN_RID(2));  in rk3576_ebc_tcon_enable()
677 	tcon_write(tcon, RK3576_EBC_WIN2_CTRL, RK3576_WIN_RID(3));  in rk3576_ebc_tcon_enable()
689 	tcon_write(tcon, RK3576_EBC_EPD_CTRL, RK3576_EINK_MODE_SWAP(1) |  in rk3576_ebc_tcon_enable()
698 	tcon_write(tcon, RK3576_EBC_DSP_START, 0);  in rk3576_ebc_tcon_enable()
704 	tcon_write(tcon, RK3576_EBC_DSP_CTRL2, RK3576_SW_BURST_CTRL | val);  in rk3576_ebc_tcon_enable()
715 	tcon_write(tcon, RK3576_EBC_DSP_CTRL,  in rk3576_ebc_tcon_enable()
719 	tcon_cfg_done(tcon);  in rk3576_ebc_tcon_enable()
721 	ret = clk_set_rate(&tcon->dclk,  in rk3576_ebc_tcon_enable()
735 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in rk3576_ebc_tcon_dsp_mode_set()  local
737 	tcon_write(tcon, RK3576_EBC_WIN1_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) |  in rk3576_ebc_tcon_dsp_mode_set()
741 	tcon_write(tcon, RK3576_EBC_WIN2_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) |  in rk3576_ebc_tcon_dsp_mode_set()
746 	tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL,  in rk3576_ebc_tcon_dsp_mode_set()
750 	tcon_update_bits(tcon, RK3576_EBC_EPD_CTRL, RK3576_THREE_WIN_MODE_MASK,  in rk3576_ebc_tcon_dsp_mode_set()
753 	tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL2, RK3576_DSP_EINK_MODE_MASK,  in rk3576_ebc_tcon_dsp_mode_set()
755 	tcon_cfg_done(tcon);  in rk3576_ebc_tcon_dsp_mode_set()
762 	struct ebc_tcon_priv *tcon = dev_get_priv(dev);  in rk3576_ebc_tcon_frame_start()  local
764 	tcon_write(tcon, RK3576_EBC_INT_STATUS, RK3576_LINE_FLAG_INT_MASK |  in rk3576_ebc_tcon_frame_start()
769 	tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL2, RK3576_DSP_FRM_TOTAL_MASK,  in rk3576_ebc_tcon_frame_start()
771 	tcon_cfg_done(tcon);  in rk3576_ebc_tcon_frame_start()
774 	tcon_write(tcon, RK3576_EBC_DSP_START, 1);  in rk3576_ebc_tcon_frame_start()