52 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_long_data_wr()  argument
93 		exynos_mipi_dsi_wr_tx_data(dsim, payload);  in exynos_mipi_dsi_long_data_wr()
97 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,  in exynos_mipi_dsi_wr_data()  argument
104 	if (dsim->state == DSIM_STATE_ULPS) {  in exynos_mipi_dsi_wr_data()
110 	delay_val = MHZ / dsim->dsim_config->esc_clk;  in exynos_mipi_dsi_wr_data()
116 	if (dsim->state == DSIM_STATE_STOP) {  in exynos_mipi_dsi_wr_data()
117 		while (!(exynos_mipi_dsi_get_fifo_state(dsim) &  in exynos_mipi_dsi_wr_data()
138 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);  in exynos_mipi_dsi_wr_data()
151 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);  in exynos_mipi_dsi_wr_data()
172 		exynos_mipi_dsi_clear_all_interrupt(dsim);  in exynos_mipi_dsi_wr_data()
173 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);  in exynos_mipi_dsi_wr_data()
192 			exynos_mipi_dsi_wr_tx_data(dsim, payload);  in exynos_mipi_dsi_wr_data()
199 			exynos_mipi_dsi_long_data_wr(dsim, data0, data1);  in exynos_mipi_dsi_wr_data()
203 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,  in exynos_mipi_dsi_wr_data()
234 int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)  in exynos_mipi_dsi_pll_on()  argument
241 		exynos_mipi_dsi_clear_interrupt(dsim);  in exynos_mipi_dsi_pll_on()
242 		exynos_mipi_dsi_enable_pll(dsim, 1);  in exynos_mipi_dsi_pll_on()
245 			if (exynos_mipi_dsi_is_pll_stable(dsim))  in exynos_mipi_dsi_pll_on()
251 		exynos_mipi_dsi_enable_pll(dsim, 0);  in exynos_mipi_dsi_pll_on()
256 unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_change_pll()  argument
287 		exynos_mipi_dsi_enable_afc(dsim, 0, 0);  in exynos_mipi_dsi_change_pll()
290 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);  in exynos_mipi_dsi_change_pll()
292 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);  in exynos_mipi_dsi_change_pll()
294 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);  in exynos_mipi_dsi_change_pll()
296 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);  in exynos_mipi_dsi_change_pll()
298 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);  in exynos_mipi_dsi_change_pll()
300 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);  in exynos_mipi_dsi_change_pll()
322 	exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);  in exynos_mipi_dsi_change_pll()
324 	exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);  in exynos_mipi_dsi_change_pll()
325 	exynos_mipi_dsi_prep_ctrl(dsim, 0);  in exynos_mipi_dsi_change_pll()
328 	exynos_mipi_dsi_pll_freq_band(dsim, freq_band);  in exynos_mipi_dsi_change_pll()
331 	exynos_mipi_dsi_pll_stable_time(dsim,  in exynos_mipi_dsi_change_pll()
332 				dsim->dsim_config->pll_stable_time);  in exynos_mipi_dsi_change_pll()
341 int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_set_clock()  argument
349 		dsim->e_clk_src = byte_clk_sel;  in exynos_mipi_dsi_set_clock()
352 		exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);  in exynos_mipi_dsi_set_clock()
356 			hs_clk = exynos_mipi_dsi_change_pll(dsim,  in exynos_mipi_dsi_set_clock()
357 				dsim->dsim_config->p, dsim->dsim_config->m,  in exynos_mipi_dsi_set_clock()
358 				dsim->dsim_config->s);  in exynos_mipi_dsi_set_clock()
365 			exynos_mipi_dsi_enable_pll_bypass(dsim, 0);  in exynos_mipi_dsi_set_clock()
366 			exynos_mipi_dsi_pll_on(dsim, 1);  in exynos_mipi_dsi_set_clock()
374 		esc_div = byte_clk / (dsim->dsim_config->esc_clk);  in exynos_mipi_dsi_set_clock()
376 			esc_div, byte_clk, dsim->dsim_config->esc_clk);  in exynos_mipi_dsi_set_clock()
378 			(byte_clk / esc_div) > dsim->dsim_config->esc_clk)  in exynos_mipi_dsi_set_clock()
386 		exynos_mipi_dsi_enable_byte_clock(dsim, 1);  in exynos_mipi_dsi_set_clock()
389 		exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);  in exynos_mipi_dsi_set_clock()
391 		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,  in exynos_mipi_dsi_set_clock()
392 			(DSIM_LANE_CLOCK | dsim->data_lane), 1);  in exynos_mipi_dsi_set_clock()
397 			(dsim->dsim_config->esc_clk / MHZ));  in exynos_mipi_dsi_set_clock()
414 		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,  in exynos_mipi_dsi_set_clock()
415 			(DSIM_LANE_CLOCK | dsim->data_lane), 0);  in exynos_mipi_dsi_set_clock()
416 		exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);  in exynos_mipi_dsi_set_clock()
419 		exynos_mipi_dsi_enable_byte_clock(dsim, 0);  in exynos_mipi_dsi_set_clock()
422 			exynos_mipi_dsi_pll_on(dsim, 0);  in exynos_mipi_dsi_set_clock()
428 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_init_dsim()  argument
430 	dsim->state = DSIM_STATE_INIT;  in exynos_mipi_dsi_init_dsim()
432 	switch (dsim->dsim_config->e_no_data_lane) {  in exynos_mipi_dsi_init_dsim()
434 		dsim->data_lane = DSIM_LANE_DATA0;  in exynos_mipi_dsi_init_dsim()
437 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;  in exynos_mipi_dsi_init_dsim()
440 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |  in exynos_mipi_dsi_init_dsim()
444 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |  in exynos_mipi_dsi_init_dsim()
452 	exynos_mipi_dsi_sw_reset(dsim);  in exynos_mipi_dsi_init_dsim()
453 	exynos_mipi_dsi_dp_dn_swap(dsim, 0);  in exynos_mipi_dsi_init_dsim()
458 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_enable_frame_done_int()  argument
462 	exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);  in exynos_mipi_dsi_enable_frame_done_int()
480 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_set_display_mode()  argument
487 	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;  in exynos_mipi_dsi_set_display_mode()
493 	if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {  in exynos_mipi_dsi_set_display_mode()
494 		if (dsim->dsim_config->auto_vertical_cnt == 0) {  in exynos_mipi_dsi_set_display_mode()
495 			exynos_mipi_dsi_set_main_disp_vporch(dsim,  in exynos_mipi_dsi_set_display_mode()
499 			exynos_mipi_dsi_set_main_disp_hporch(dsim,  in exynos_mipi_dsi_set_display_mode()
502 			exynos_mipi_dsi_set_main_disp_sync_area(dsim,  in exynos_mipi_dsi_set_display_mode()
508 	exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,  in exynos_mipi_dsi_set_display_mode()
511 	exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);  in exynos_mipi_dsi_set_display_mode()
519 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_init_link()  argument
523 	switch (dsim->state) {  in exynos_mipi_dsi_init_link()
525 		exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);  in exynos_mipi_dsi_init_link()
528 		exynos_mipi_dsi_init_config(dsim);  in exynos_mipi_dsi_init_link()
529 		exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);  in exynos_mipi_dsi_init_link()
530 		exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);  in exynos_mipi_dsi_init_link()
533 		exynos_mipi_dsi_set_clock(dsim,  in exynos_mipi_dsi_init_link()
534 					dsim->dsim_config->e_byte_clk, 1);  in exynos_mipi_dsi_init_link()
537 		while (!(exynos_mipi_dsi_is_lane_state(dsim))) {  in exynos_mipi_dsi_init_link()
547 		dsim->state = DSIM_STATE_STOP;  in exynos_mipi_dsi_init_link()
550 		exynos_mipi_dsi_set_stop_state_counter(dsim,  in exynos_mipi_dsi_init_link()
551 			dsim->dsim_config->stop_holding_cnt);  in exynos_mipi_dsi_init_link()
552 		exynos_mipi_dsi_set_bta_timeout(dsim,  in exynos_mipi_dsi_init_link()
553 			dsim->dsim_config->bta_timeout);  in exynos_mipi_dsi_init_link()
554 		exynos_mipi_dsi_set_lpdr_timeout(dsim,  in exynos_mipi_dsi_init_link()
555 			dsim->dsim_config->rx_timeout);  in exynos_mipi_dsi_init_link()
566 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_set_hs_enable()  argument
568 	if (dsim->state == DSIM_STATE_STOP) {  in exynos_mipi_dsi_set_hs_enable()
569 		if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {  in exynos_mipi_dsi_set_hs_enable()
570 			dsim->state = DSIM_STATE_HSCLKEN;  in exynos_mipi_dsi_set_hs_enable()
573 			exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_hs_enable()
574 			exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_hs_enable()
576 			exynos_mipi_dsi_enable_hs_clock(dsim, 1);  in exynos_mipi_dsi_set_hs_enable()
587 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,  in exynos_mipi_dsi_set_data_transfer_mode()  argument
591 		if (dsim->state != DSIM_STATE_HSCLKEN) {  in exynos_mipi_dsi_set_data_transfer_mode()
596 		exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_data_transfer_mode()
598 		if (dsim->state == DSIM_STATE_INIT || dsim->state ==  in exynos_mipi_dsi_set_data_transfer_mode()
604 		exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);  in exynos_mipi_dsi_set_data_transfer_mode()
610 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_get_frame_done_status()  argument
612 	return _exynos_mipi_dsi_get_frame_done_status(dsim);  in exynos_mipi_dsi_get_frame_done_status()
615 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)  in exynos_mipi_dsi_clear_frame_done()  argument
617 	_exynos_mipi_dsi_clear_frame_done(dsim);  in exynos_mipi_dsi_clear_frame_done()