355 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)  in inno_write()  function
377 	inno_write(inno, reg, tmp);  in inno_update_bits()
604 	inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_power_on()
623 		inno_write(inno, 0xef + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3228_power_on()
682 	inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_pre_pll_update()
725 	inno_write(inno, 0x01, 0x07);  in inno_hdmi_phy_rk3328_init()
726 	inno_write(inno, 0x02, 0x91);  in inno_hdmi_phy_rk3328_init()
742 	inno_write(inno, 0xac, val);  in inno_hdmi_phy_rk3328_power_on()
744 		inno_write(inno, 0xaa, 2);  in inno_hdmi_phy_rk3328_power_on()
746 		inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3328_power_on()
749 		inno_write(inno, 0xad, val);  in inno_hdmi_phy_rk3328_power_on()
751 		inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3328_power_on()
752 		inno_write(inno, 0xaa, 0x0e);  in inno_hdmi_phy_rk3328_power_on()
756 		inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);  in inno_hdmi_phy_rk3328_power_on()
765 	inno_write(inno, 0xc8, 0);  in inno_hdmi_phy_rk3328_power_on()
766 	inno_write(inno, 0xc9, 0);  in inno_hdmi_phy_rk3328_power_on()
767 	inno_write(inno, 0xca, 0);  in inno_hdmi_phy_rk3328_power_on()
768 	inno_write(inno, 0xcb, 0);  in inno_hdmi_phy_rk3328_power_on()
773 		inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80);  in inno_hdmi_phy_rk3328_power_on()
774 		inno_write(inno, 0xc6, val & 0xff);  in inno_hdmi_phy_rk3328_power_on()
775 		inno_write(inno, 0xc7, 3 << 1);  in inno_hdmi_phy_rk3328_power_on()
776 		inno_write(inno, 0xc5, ((val >> 8) & 0xff));  in inno_hdmi_phy_rk3328_power_on()
778 		inno_write(inno, 0xc5, 0x81);  in inno_hdmi_phy_rk3328_power_on()
782 		inno_write(inno, 0xc8, 0x30);  in inno_hdmi_phy_rk3328_power_on()
783 		inno_write(inno, 0xc9, 0x10);  in inno_hdmi_phy_rk3328_power_on()
784 		inno_write(inno, 0xca, 0x10);  in inno_hdmi_phy_rk3328_power_on()
785 		inno_write(inno, 0xcb, 0x10);  in inno_hdmi_phy_rk3328_power_on()
787 		inno_write(inno, 0xc5, 0x81);  in inno_hdmi_phy_rk3328_power_on()
792 	inno_write(inno, 0xd8, (val >> 8) & 0xff);  in inno_hdmi_phy_rk3328_power_on()
793 	inno_write(inno, 0xd9, val & 0xff);  in inno_hdmi_phy_rk3328_power_on()
799 	inno_write(inno, 0xb2, 0x0f);  in inno_hdmi_phy_rk3328_power_on()
822 	inno_write(inno, 0xb2, 0);  in inno_hdmi_phy_rk3328_power_off()
839 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3328_pre_pll_update()
844 	inno_write(inno, 0xa2, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
845 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3328_pre_pll_update()
848 	inno_write(inno, 0xa5, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
851 	inno_write(inno, 0xa6, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
855 	inno_write(inno, 0xa4, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
859 		inno_write(inno, 0xd3, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
861 		inno_write(inno, 0xd2, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
863 		inno_write(inno, 0xd1, val);  in inno_hdmi_phy_rk3328_pre_pll_update()
865 		inno_write(inno, 0xd3, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
866 		inno_write(inno, 0xd2, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
867 		inno_write(inno, 0xd1, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
935 	inno_write(inno, 0xab, val);  in inno_hdmi_phy_rk3528_power_on()
938 		inno_write(inno, 0xad, 0x8);  in inno_hdmi_phy_rk3528_power_on()
939 		inno_write(inno, 0xaa, 2);  in inno_hdmi_phy_rk3528_power_on()
942 		inno_write(inno, 0xad, val);  in inno_hdmi_phy_rk3528_power_on()
943 		inno_write(inno, 0xaa, 0x0e);  in inno_hdmi_phy_rk3528_power_on()
947 	inno_write(inno, 0xac, val);  in inno_hdmi_phy_rk3528_power_on()
953 	inno_write(inno, 0xbf, val);  in inno_hdmi_phy_rk3528_power_on()
957 	inno_write(inno, 0xc0, val);  in inno_hdmi_phy_rk3528_power_on()
960 	inno_write(inno, 0xb5, phy_cfg->regs[2]);  in inno_hdmi_phy_rk3528_power_on()
961 	inno_write(inno, 0xb6, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
962 	inno_write(inno, 0xb7, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
963 	inno_write(inno, 0xb8, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
966 	inno_write(inno, 0xbb, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
967 	inno_write(inno, 0xbc, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
968 	inno_write(inno, 0xbd, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
971 	inno_write(inno, 0xb4, 0x7);  in inno_hdmi_phy_rk3528_power_on()
974 	inno_write(inno, 0xbe, 0x70);  in inno_hdmi_phy_rk3528_power_on()
976 	inno_write(inno, 0xb2, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
989 	inno_write(inno, 0xc7, phy_cfg->regs[5]);  in inno_hdmi_phy_rk3528_power_on()
990 	inno_write(inno, 0xc5, phy_cfg->regs[6]);  in inno_hdmi_phy_rk3528_power_on()
991 	inno_write(inno, 0xc8, phy_cfg->regs[7]);  in inno_hdmi_phy_rk3528_power_on()
992 	inno_write(inno, 0xc9, phy_cfg->regs[8]);  in inno_hdmi_phy_rk3528_power_on()
993 	inno_write(inno, 0xca, phy_cfg->regs[8]);  in inno_hdmi_phy_rk3528_power_on()
994 	inno_write(inno, 0xcb, phy_cfg->regs[8]);  in inno_hdmi_phy_rk3528_power_on()
999 	inno_write(inno, 0xd8, (temp >> 8) & 0xff);  in inno_hdmi_phy_rk3528_power_on()
1000 	inno_write(inno, 0xd9, temp & 0xff);  in inno_hdmi_phy_rk3528_power_on()
1009 	inno_write(inno, 0x05, 0x22);  in inno_hdmi_phy_rk3528_power_on()
1010 	inno_write(inno, 0x07, 0x22);  in inno_hdmi_phy_rk3528_power_on()
1011 	inno_write(inno, 0xcc, 0x0f);  in inno_hdmi_phy_rk3528_power_on()
1019 	inno_write(inno, 0xb2, 0);  in inno_hdmi_phy_rk3528_power_off()
1026 	inno_write(inno, 0x05, 0);  in inno_hdmi_phy_rk3528_power_off()
1027 	inno_write(inno, 0x07, 0);  in inno_hdmi_phy_rk3528_power_off()
1036 	inno_write(inno, 0x02, 0x81);  in inno_hdmi_phy_rk3528_init()
1046 	inno_write(inno, 0xcc, 0x0f);  in inno_hdmi_phy_rk3528_pre_pll_update()
1052 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3528_pre_pll_update()
1057 	inno_write(inno, 0xa2, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1058 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3528_pre_pll_update()
1061 	inno_write(inno, 0xa5, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1064 	inno_write(inno, 0xa6, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1068 	inno_write(inno, 0xa4, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1072 		inno_write(inno, 0xd3, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1074 		inno_write(inno, 0xd2, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1076 		inno_write(inno, 0xd1, val);  in inno_hdmi_phy_rk3528_pre_pll_update()
1078 		inno_write(inno, 0xd3, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1079 		inno_write(inno, 0xd2, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1080 		inno_write(inno, 0xd1, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()