369 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,  in inno_update_bits()  function
532 		inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK,  in inno_hdmi_phy_clk_prepare()
535 		inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_clk_prepare()
574 	inno_update_bits(inno, 0x01, m, v);  in inno_hdmi_phy_rk3228_init()
575 	inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN);  in inno_hdmi_phy_rk3228_init()
578 	inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL);  in inno_hdmi_phy_rk3228_init()
590 	inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE);  in inno_hdmi_phy_rk3228_power_on()
593 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_on()
594 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_on()
599 	inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
603 	inno_update_bits(inno, 0xeb, m, v);  in inno_hdmi_phy_rk3228_power_on()
610 		inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
615 		inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
619 		inno_update_bits(inno, 0xeb, m, v);  in inno_hdmi_phy_rk3228_power_on()
626 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_power_on()
627 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_power_on()
630 	inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
633 	inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
651 	inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
658 	inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE);  in inno_hdmi_phy_rk3228_power_off()
661 	inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE);  in inno_hdmi_phy_rk3228_power_off()
664 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_off()
675 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_pre_pll_update()
680 	inno_update_bits(inno, 0xe2, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
687 	inno_update_bits(inno, 0xe4, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
692 	inno_update_bits(inno, 0xe5, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
699 	inno_update_bits(inno, 0xe6, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
702 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_pre_pll_update()
737 	inno_update_bits(inno, 0x02, 1, 0);  in inno_hdmi_phy_rk3328_power_on()
739 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3328_power_on()
796 	inno_update_bits(inno, 0xaa, 1, 0);  in inno_hdmi_phy_rk3328_power_on()
798 	inno_update_bits(inno, 0xb0, 4, 4);  in inno_hdmi_phy_rk3328_power_on()
814 	inno_update_bits(inno, 0x02, 1, 1);  in inno_hdmi_phy_rk3328_power_on()
824 	inno_update_bits(inno, 0xb0, 4, 0);  in inno_hdmi_phy_rk3328_power_off()
826 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3328_power_off()
836 	inno_update_bits(inno, 0xa0, 1, 1);  in inno_hdmi_phy_rk3328_pre_pll_update()
838 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3328_pre_pll_update()
871 	inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
932 	inno_update_bits(inno, 0xaa, 1, 0);  in inno_hdmi_phy_rk3528_power_on()
949 	inno_update_bits(inno, 0xad, BIT(4), val);  in inno_hdmi_phy_rk3528_power_on()
1005 	inno_update_bits(inno, 0x02, 1, 0);  in inno_hdmi_phy_rk3528_power_on()
1006 	inno_update_bits(inno, 0x02, 1, 1);  in inno_hdmi_phy_rk3528_power_on()
1021 	inno_update_bits(inno, 0xb0, 4, 0);  in inno_hdmi_phy_rk3528_power_off()
1023 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3528_power_off()
1045 	inno_update_bits(inno, 0xb0, 4, 4);  in inno_hdmi_phy_rk3528_pre_pll_update()
1049 	inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1051 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3528_pre_pll_update()