Lines Matching refs:inno
200 void (*init)(struct inno_hdmi_phy *inno);
201 int (*power_on)(struct inno_hdmi_phy *inno,
204 void (*power_off)(struct inno_hdmi_phy *inno);
205 int (*pre_pll_update)(struct inno_hdmi_phy *inno,
207 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno,
355 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) in inno_write() argument
357 writel(val, inno->regs + (reg * 4)); in inno_write()
360 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) in inno_read() argument
364 val = readl(inno->regs + (reg * 4)); in inno_read()
369 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, in inno_update_bits() argument
374 orig = inno_read(inno, reg); in inno_update_bits()
377 inno_write(inno, reg, tmp); in inno_update_bits()
380 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, in inno_hdmi_phy_get_tmdsclk() argument
385 switch (inno->bus_width) { in inno_hdmi_phy_get_tmdsclk()
453 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_power_on() local
455 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_power_on()
458 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on()
459 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); in inno_hdmi_phy_power_on()
464 if (inno->phy_cfg) in inno_hdmi_phy_power_on()
465 phy_cfg = inno->phy_cfg; in inno_hdmi_phy_power_on()
472 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && in inno_hdmi_phy_power_on()
475 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && in inno_hdmi_phy_power_on()
478 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528) in inno_hdmi_phy_power_on()
496 if (inno->plat_data->ops->power_on) in inno_hdmi_phy_power_on()
497 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
505 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_power_off() local
507 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_power_off()
510 if (inno->plat_data->ops->power_off) in inno_hdmi_phy_power_off()
511 inno->plat_data->ops->power_off(inno); in inno_hdmi_phy_power_off()
517 static int inno_hdmi_phy_clk_is_prepared(struct inno_hdmi_phy *inno) in inno_hdmi_phy_clk_is_prepared() argument
521 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_is_prepared()
522 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK; in inno_hdmi_phy_clk_is_prepared()
524 status = inno_read(inno, 0xa0) & 1; in inno_hdmi_phy_clk_is_prepared()
529 static int inno_hdmi_phy_clk_prepare(struct inno_hdmi_phy *inno) in inno_hdmi_phy_clk_prepare() argument
531 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_prepare()
532 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, in inno_hdmi_phy_clk_prepare()
535 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_clk_prepare()
540 static int inno_hdmi_phy_clk_set_rate(struct inno_hdmi_phy *inno, in inno_hdmi_phy_clk_set_rate() argument
544 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); in inno_hdmi_phy_clk_set_rate()
555 if (inno->plat_data->ops->pre_pll_update) in inno_hdmi_phy_clk_set_rate()
556 inno->plat_data->ops->pre_pll_update(inno, cfg); in inno_hdmi_phy_clk_set_rate()
558 inno->pixclock = rate; in inno_hdmi_phy_clk_set_rate()
563 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3228_init() argument
574 inno_update_bits(inno, 0x01, m, v); in inno_hdmi_phy_rk3228_init()
575 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN); in inno_hdmi_phy_rk3228_init()
578 inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL); in inno_hdmi_phy_rk3228_init()
582 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3228_power_on() argument
590 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE); in inno_hdmi_phy_rk3228_power_on()
593 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
594 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
599 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
603 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
604 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
610 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
615 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
619 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
623 inno_write(inno, 0xef + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3228_power_on()
626 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP); in inno_hdmi_phy_rk3228_power_on()
627 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); in inno_hdmi_phy_rk3228_power_on()
630 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE); in inno_hdmi_phy_rk3228_power_on()
633 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE); in inno_hdmi_phy_rk3228_power_on()
637 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) { in inno_hdmi_phy_rk3228_power_on()
651 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE); in inno_hdmi_phy_rk3228_power_on()
655 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3228_power_off() argument
658 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE); in inno_hdmi_phy_rk3228_power_off()
661 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE); in inno_hdmi_phy_rk3228_power_off()
664 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_off()
668 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3228_pre_pll_update() argument
675 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_pre_pll_update()
680 inno_update_bits(inno, 0xe2, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
682 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_pre_pll_update()
687 inno_update_bits(inno, 0xe4, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
692 inno_update_bits(inno, 0xe5, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
699 inno_update_bits(inno, 0xe6, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
702 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); in inno_hdmi_phy_rk3228_pre_pll_update()
706 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) { in inno_hdmi_phy_rk3228_pre_pll_update()
719 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3328_init() argument
725 inno_write(inno, 0x01, 0x07); in inno_hdmi_phy_rk3328_init()
726 inno_write(inno, 0x02, 0x91); in inno_hdmi_phy_rk3328_init()
730 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3328_power_on() argument
737 inno_update_bits(inno, 0x02, 1, 0); in inno_hdmi_phy_rk3328_power_on()
739 inno_update_bits(inno, 0xaa, 1, 1); in inno_hdmi_phy_rk3328_power_on()
742 inno_write(inno, 0xac, val); in inno_hdmi_phy_rk3328_power_on()
744 inno_write(inno, 0xaa, 2); in inno_hdmi_phy_rk3328_power_on()
746 inno_write(inno, 0xab, val); in inno_hdmi_phy_rk3328_power_on()
749 inno_write(inno, 0xad, val); in inno_hdmi_phy_rk3328_power_on()
751 inno_write(inno, 0xab, val); in inno_hdmi_phy_rk3328_power_on()
752 inno_write(inno, 0xaa, 0x0e); in inno_hdmi_phy_rk3328_power_on()
756 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); in inno_hdmi_phy_rk3328_power_on()
765 inno_write(inno, 0xc8, 0); in inno_hdmi_phy_rk3328_power_on()
766 inno_write(inno, 0xc9, 0); in inno_hdmi_phy_rk3328_power_on()
767 inno_write(inno, 0xca, 0); in inno_hdmi_phy_rk3328_power_on()
768 inno_write(inno, 0xcb, 0); in inno_hdmi_phy_rk3328_power_on()
773 inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80); in inno_hdmi_phy_rk3328_power_on()
774 inno_write(inno, 0xc6, val & 0xff); in inno_hdmi_phy_rk3328_power_on()
775 inno_write(inno, 0xc7, 3 << 1); in inno_hdmi_phy_rk3328_power_on()
776 inno_write(inno, 0xc5, ((val >> 8) & 0xff)); in inno_hdmi_phy_rk3328_power_on()
778 inno_write(inno, 0xc5, 0x81); in inno_hdmi_phy_rk3328_power_on()
782 inno_write(inno, 0xc8, 0x30); in inno_hdmi_phy_rk3328_power_on()
783 inno_write(inno, 0xc9, 0x10); in inno_hdmi_phy_rk3328_power_on()
784 inno_write(inno, 0xca, 0x10); in inno_hdmi_phy_rk3328_power_on()
785 inno_write(inno, 0xcb, 0x10); in inno_hdmi_phy_rk3328_power_on()
787 inno_write(inno, 0xc5, 0x81); in inno_hdmi_phy_rk3328_power_on()
792 inno_write(inno, 0xd8, (val >> 8) & 0xff); in inno_hdmi_phy_rk3328_power_on()
793 inno_write(inno, 0xd9, val & 0xff); in inno_hdmi_phy_rk3328_power_on()
796 inno_update_bits(inno, 0xaa, 1, 0); in inno_hdmi_phy_rk3328_power_on()
798 inno_update_bits(inno, 0xb0, 4, 4); in inno_hdmi_phy_rk3328_power_on()
799 inno_write(inno, 0xb2, 0x0f); in inno_hdmi_phy_rk3328_power_on()
803 if (inno_read(inno, 0xaf) & 1) in inno_hdmi_phy_rk3328_power_on()
807 if (!(inno_read(inno, 0xaf) & 1)) { in inno_hdmi_phy_rk3328_power_on()
814 inno_update_bits(inno, 0x02, 1, 1); in inno_hdmi_phy_rk3328_power_on()
819 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3328_power_off() argument
822 inno_write(inno, 0xb2, 0); in inno_hdmi_phy_rk3328_power_off()
824 inno_update_bits(inno, 0xb0, 4, 0); in inno_hdmi_phy_rk3328_power_off()
826 inno_update_bits(inno, 0xaa, 1, 1); in inno_hdmi_phy_rk3328_power_off()
830 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3328_pre_pll_update() argument
836 inno_update_bits(inno, 0xa0, 1, 1); in inno_hdmi_phy_rk3328_pre_pll_update()
838 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3328_pre_pll_update()
839 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3328_pre_pll_update()
844 inno_write(inno, 0xa2, val); in inno_hdmi_phy_rk3328_pre_pll_update()
845 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3328_pre_pll_update()
848 inno_write(inno, 0xa5, val); in inno_hdmi_phy_rk3328_pre_pll_update()
851 inno_write(inno, 0xa6, val); in inno_hdmi_phy_rk3328_pre_pll_update()
855 inno_write(inno, 0xa4, val); in inno_hdmi_phy_rk3328_pre_pll_update()
859 inno_write(inno, 0xd3, val); in inno_hdmi_phy_rk3328_pre_pll_update()
861 inno_write(inno, 0xd2, val); in inno_hdmi_phy_rk3328_pre_pll_update()
863 inno_write(inno, 0xd1, val); in inno_hdmi_phy_rk3328_pre_pll_update()
865 inno_write(inno, 0xd3, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
866 inno_write(inno, 0xd2, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
867 inno_write(inno, 0xd1, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
871 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_rk3328_pre_pll_update()
875 if (inno_read(inno, 0xa9) & 1) in inno_hdmi_phy_rk3328_pre_pll_update()
888 inno_hdmi_3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, in inno_hdmi_3328_phy_pll_recalc_rate() argument
896 nd = inno_read(inno, 0xa1) & 0x3f; in inno_hdmi_3328_phy_pll_recalc_rate()
897 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); in inno_hdmi_3328_phy_pll_recalc_rate()
899 if ((inno_read(inno, 0xa2) & 0x30) == 0) { in inno_hdmi_3328_phy_pll_recalc_rate()
900 frac = inno_read(inno, 0xd3) | in inno_hdmi_3328_phy_pll_recalc_rate()
901 (inno_read(inno, 0xd2) << 8) | in inno_hdmi_3328_phy_pll_recalc_rate()
902 (inno_read(inno, 0xd1) << 16); in inno_hdmi_3328_phy_pll_recalc_rate()
905 if (inno_read(inno, 0xa0) & 2) { in inno_hdmi_3328_phy_pll_recalc_rate()
908 no_a = inno_read(inno, 0xa5) & 0x1f; in inno_hdmi_3328_phy_pll_recalc_rate()
909 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; in inno_hdmi_3328_phy_pll_recalc_rate()
910 no_c = (1 << ((inno_read(inno, 0xa6) >> 5) & 7)); in inno_hdmi_3328_phy_pll_recalc_rate()
911 no_d = inno_read(inno, 0xa6) & 0x1f; in inno_hdmi_3328_phy_pll_recalc_rate()
917 inno->pixclock = rate; in inno_hdmi_3328_phy_pll_recalc_rate()
923 inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3528_power_on() argument
929 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); in inno_hdmi_phy_rk3528_power_on()
932 inno_update_bits(inno, 0xaa, 1, 0); in inno_hdmi_phy_rk3528_power_on()
935 inno_write(inno, 0xab, val); in inno_hdmi_phy_rk3528_power_on()
938 inno_write(inno, 0xad, 0x8); in inno_hdmi_phy_rk3528_power_on()
939 inno_write(inno, 0xaa, 2); in inno_hdmi_phy_rk3528_power_on()
942 inno_write(inno, 0xad, val); in inno_hdmi_phy_rk3528_power_on()
943 inno_write(inno, 0xaa, 0x0e); in inno_hdmi_phy_rk3528_power_on()
947 inno_write(inno, 0xac, val); in inno_hdmi_phy_rk3528_power_on()
949 inno_update_bits(inno, 0xad, BIT(4), val); in inno_hdmi_phy_rk3528_power_on()
953 inno_write(inno, 0xbf, val); in inno_hdmi_phy_rk3528_power_on()
957 inno_write(inno, 0xc0, val); in inno_hdmi_phy_rk3528_power_on()
960 inno_write(inno, 0xb5, phy_cfg->regs[2]); in inno_hdmi_phy_rk3528_power_on()
961 inno_write(inno, 0xb6, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
962 inno_write(inno, 0xb7, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
963 inno_write(inno, 0xb8, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
966 inno_write(inno, 0xbb, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
967 inno_write(inno, 0xbc, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
968 inno_write(inno, 0xbd, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
971 inno_write(inno, 0xb4, 0x7); in inno_hdmi_phy_rk3528_power_on()
974 inno_write(inno, 0xbe, 0x70); in inno_hdmi_phy_rk3528_power_on()
976 inno_write(inno, 0xb2, 0x0f); in inno_hdmi_phy_rk3528_power_on()
979 if (inno_read(inno, 0xaf) & 1) in inno_hdmi_phy_rk3528_power_on()
983 if (!(inno_read(inno, 0xaf) & 1)) { in inno_hdmi_phy_rk3528_power_on()
984 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n"); in inno_hdmi_phy_rk3528_power_on()
989 inno_write(inno, 0xc7, phy_cfg->regs[5]); in inno_hdmi_phy_rk3528_power_on()
990 inno_write(inno, 0xc5, phy_cfg->regs[6]); in inno_hdmi_phy_rk3528_power_on()
991 inno_write(inno, 0xc8, phy_cfg->regs[7]); in inno_hdmi_phy_rk3528_power_on()
992 inno_write(inno, 0xc9, phy_cfg->regs[8]); in inno_hdmi_phy_rk3528_power_on()
993 inno_write(inno, 0xca, phy_cfg->regs[8]); in inno_hdmi_phy_rk3528_power_on()
994 inno_write(inno, 0xcb, phy_cfg->regs[8]); in inno_hdmi_phy_rk3528_power_on()
999 inno_write(inno, 0xd8, (temp >> 8) & 0xff); in inno_hdmi_phy_rk3528_power_on()
1000 inno_write(inno, 0xd9, temp & 0xff); in inno_hdmi_phy_rk3528_power_on()
1005 inno_update_bits(inno, 0x02, 1, 0); in inno_hdmi_phy_rk3528_power_on()
1006 inno_update_bits(inno, 0x02, 1, 1); in inno_hdmi_phy_rk3528_power_on()
1009 inno_write(inno, 0x05, 0x22); in inno_hdmi_phy_rk3528_power_on()
1010 inno_write(inno, 0x07, 0x22); in inno_hdmi_phy_rk3528_power_on()
1011 inno_write(inno, 0xcc, 0x0f); in inno_hdmi_phy_rk3528_power_on()
1016 static void inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3528_power_off() argument
1019 inno_write(inno, 0xb2, 0); in inno_hdmi_phy_rk3528_power_off()
1021 inno_update_bits(inno, 0xb0, 4, 0); in inno_hdmi_phy_rk3528_power_off()
1023 inno_update_bits(inno, 0xaa, 1, 1); in inno_hdmi_phy_rk3528_power_off()
1026 inno_write(inno, 0x05, 0); in inno_hdmi_phy_rk3528_power_off()
1027 inno_write(inno, 0x07, 0); in inno_hdmi_phy_rk3528_power_off()
1030 static void inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3528_init() argument
1036 inno_write(inno, 0x02, 0x81); in inno_hdmi_phy_rk3528_init()
1040 inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3528_pre_pll_update() argument
1045 inno_update_bits(inno, 0xb0, 4, 4); in inno_hdmi_phy_rk3528_pre_pll_update()
1046 inno_write(inno, 0xcc, 0x0f); in inno_hdmi_phy_rk3528_pre_pll_update()
1049 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1051 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3528_pre_pll_update()
1052 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3528_pre_pll_update()
1057 inno_write(inno, 0xa2, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1058 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3528_pre_pll_update()
1061 inno_write(inno, 0xa5, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1064 inno_write(inno, 0xa6, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1068 inno_write(inno, 0xa4, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1072 inno_write(inno, 0xd3, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1074 inno_write(inno, 0xd2, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1076 inno_write(inno, 0xd1, val); in inno_hdmi_phy_rk3528_pre_pll_update()
1078 inno_write(inno, 0xd3, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1079 inno_write(inno, 0xd2, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1080 inno_write(inno, 0xd1, 0); in inno_hdmi_phy_rk3528_pre_pll_update()
1085 if (inno_read(inno, 0xa9) & 1) in inno_hdmi_phy_rk3528_pre_pll_update()
1090 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3528_pre_pll_update()
1098 inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, in inno_hdmi_rk3528_phy_pll_recalc_rate() argument
1106 nd = inno_read(inno, 0xa1) & 0x3f; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1107 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1109 if ((inno_read(inno, 0xa2) & 0x30) == 0) { in inno_hdmi_rk3528_phy_pll_recalc_rate()
1110 frac = inno_read(inno, 0xd3) | in inno_hdmi_rk3528_phy_pll_recalc_rate()
1111 (inno_read(inno, 0xd2) << 8) | in inno_hdmi_rk3528_phy_pll_recalc_rate()
1112 (inno_read(inno, 0xd1) << 16); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1115 if (inno_read(inno, 0xa0) & 2) { in inno_hdmi_rk3528_phy_pll_recalc_rate()
1118 no_a = inno_read(inno, 0xa5) & 0x1f; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1119 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1120 no_d = inno_read(inno, 0xa6) & 0x1f; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1128 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1130 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1139 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, in inno_hdmi_update_phy_table() argument
1226 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_init() local
1229 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_init()
1237 inno->regs = (void *)RK3528_HDMIPHY_BASE; in inno_hdmi_phy_init()
1239 inno->regs = dev_read_addr_ptr(dev); in inno_hdmi_phy_init()
1240 inno->node = dev->node; in inno_hdmi_phy_init()
1242 if (!inno->regs) { in inno_hdmi_phy_init()
1254 inno->plat_data = inno_hdmi_phy_of_match[i].data; in inno_hdmi_phy_init()
1276 inno->phy_cfg = malloc(val + PHY_TAB_LEN); in inno_hdmi_phy_init()
1277 if (!inno->phy_cfg) { in inno_hdmi_phy_init()
1284 ret = inno_hdmi_update_phy_table(inno, phy_config, in inno_hdmi_phy_init()
1285 inno->phy_cfg, in inno_hdmi_phy_init()
1300 if (!inno->plat_data || !inno->plat_data->ops) in inno_hdmi_phy_init()
1303 if (inno->plat_data->ops->init) in inno_hdmi_phy_init()
1304 inno->plat_data->ops->init(inno); in inno_hdmi_phy_init()
1313 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_set_pll() local
1315 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_set_pll()
1319 if (!inno) in inno_hdmi_phy_set_pll()
1320 inno = g_inno; in inno_hdmi_phy_set_pll()
1322 inno_hdmi_phy_clk_prepare(inno); in inno_hdmi_phy_set_pll()
1323 inno_hdmi_phy_clk_is_prepared(inno); in inno_hdmi_phy_set_pll()
1324 inno_hdmi_phy_clk_set_rate(inno, rate); in inno_hdmi_phy_set_pll()
1332 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_set_bus_width() local
1334 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_set_bus_width()
1337 inno->bus_width = bus_width; in inno_hdmi_phy_set_bus_width()
1346 struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data; in inno_hdmi_phy_clk_round_rate() local
1348 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); in inno_hdmi_phy_clk_round_rate()
1352 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); in inno_hdmi_phy_clk_round_rate()
1362 if ((inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && in inno_hdmi_phy_clk_round_rate()
1371 if (!inno->phy_cfg) in inno_hdmi_phy_clk_round_rate()
1375 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { in inno_hdmi_phy_clk_round_rate()
1376 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) in inno_hdmi_phy_clk_round_rate()
1380 if (inno->phy_cfg[i].tmdsclock == ~0UL) in inno_hdmi_phy_clk_round_rate()
1418 struct inno_hdmi_phy *inno = malloc(sizeof(struct inno_hdmi_phy)); in inno_spl_hdmi_phy_probe() local
1420 memset(inno, 0, sizeof(*inno)); in inno_spl_hdmi_phy_probe()
1421 g_inno = inno; in inno_spl_hdmi_phy_probe()
1424 state->conn_state.connector->phy->data = (void *)inno; in inno_spl_hdmi_phy_probe()
1430 struct inno_hdmi_phy *inno = dev_get_priv(dev); in inno_hdmi_phy_probe() local
1434 inno->dev = dev; in inno_hdmi_phy_probe()
1437 g_inno = inno; in inno_hdmi_phy_probe()