Lines Matching refs:dsi
203 static inline int dsi_write(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_write() argument
208 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in dsi_write()
213 static inline int dsi_read(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_read() argument
218 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in dsi_read()
224 const struct rk628_dsi *dsi, in dsi_update_bits() argument
229 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in dsi_update_bits()
293 const struct rk628_dsi *dsi) in genif_wait_w_pld_fifo_not_full() argument
299 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in genif_wait_w_pld_fifo_not_full()
312 const struct rk628_dsi *dsi) in genif_wait_cmd_fifo_not_full() argument
318 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in genif_wait_cmd_fifo_not_full()
331 static int genif_wait_write_fifo_empty(struct rk628 *rk628, const struct rk628_dsi *dsi) in genif_wait_write_fifo_empty() argument
338 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in genif_wait_write_fifo_empty()
353 const struct rk628_dsi *dsi, in rk628_dsi_read_from_fifo() argument
363 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in rk628_dsi_read_from_fifo()
375 dsi_read(rk628, dsi, DSI_CMD_PKT_STATUS, &val); in rk628_dsi_read_from_fifo()
383 dsi_read(rk628, dsi, DSI_GEN_PLD_DATA, &val); in rk628_dsi_read_from_fifo()
526 static int rk628_dsi_transfer(struct rk628 *rk628, const struct rk628_dsi *dsi, in rk628_dsi_transfer() argument
534 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, in rk628_dsi_transfer()
538 dsi_update_bits(rk628, dsi, DSI_VID_MODE_CFG, in rk628_dsi_transfer()
541 dsi_update_bits(rk628, dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); in rk628_dsi_transfer()
542 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL, in rk628_dsi_transfer()
552 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, in rk628_dsi_transfer()
557 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, in rk628_dsi_transfer()
562 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, in rk628_dsi_transfer()
567 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, in rk628_dsi_transfer()
572 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, in rk628_dsi_transfer()
577 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, in rk628_dsi_transfer()
582 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, in rk628_dsi_transfer()
587 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, in rk628_dsi_transfer()
592 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, in rk628_dsi_transfer()
597 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, in rk628_dsi_transfer()
601 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, in rk628_dsi_transfer()
605 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, in rk628_dsi_transfer()
630 ret = genif_wait_w_pld_fifo_not_full(rk628, dsi); in rk628_dsi_transfer()
636 dsi_write(rk628, dsi, DSI_GEN_PLD_DATA, val); in rk628_dsi_transfer()
654 dsi_write(rk628, dsi, DSI_GEN_PLD_DATA, val); in rk628_dsi_transfer()
658 ret = genif_wait_cmd_fifo_not_full(rk628, dsi); in rk628_dsi_transfer()
665 dsi_write(rk628, dsi, DSI_GEN_HDR, val); in rk628_dsi_transfer()
667 ret = genif_wait_write_fifo_empty(rk628, dsi); in rk628_dsi_transfer()
672 ret = rk628_dsi_read_from_fifo(rk628, dsi, msg); in rk628_dsi_transfer()
677 if (dsi->slave) { in rk628_dsi_transfer()
689 const struct rk628_dsi *dsi = &rk628->dsi0; in rk628_mipi_dsi_generic_write() local
693 msg.channel = dsi->channel; in rk628_mipi_dsi_generic_write()
714 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_LPM) in rk628_mipi_dsi_generic_write()
717 return rk628_dsi_transfer(rk628, dsi, &msg); in rk628_mipi_dsi_generic_write()
723 const struct rk628_dsi *dsi = &rk628->dsi0; in rk628_mipi_dsi_dcs_write_buffer() local
727 msg.channel = dsi->channel; in rk628_mipi_dsi_dcs_write_buffer()
746 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_LPM) in rk628_mipi_dsi_dcs_write_buffer()
749 return rk628_dsi_transfer(rk628, dsi, &msg); in rk628_mipi_dsi_dcs_write_buffer()
755 const struct rk628_dsi *dsi = &rk628->dsi0; in rk628_mipi_dsi_dcs_read() local
759 msg.channel = dsi->channel; in rk628_mipi_dsi_dcs_read()
766 return rk628_dsi_transfer(rk628, dsi, &msg); in rk628_mipi_dsi_dcs_read()
810 static u32 rk628_dsi_get_lane_rate(const struct rk628_dsi *dsi) in rk628_dsi_get_lane_rate() argument
812 const struct drm_display_mode *mode = &dsi->rk628->dst_mode; in rk628_dsi_get_lane_rate()
818 dsi_np = dev_read_subnode(dsi->rk628->dev, "rk628-dsi-out"); in rk628_dsi_get_lane_rate()
820 dsi_np = dev_read_subnode(dsi->rk628->dev, "rk628-dsi"); in rk628_dsi_get_lane_rate()
824 bpp = dsi->bpp; in rk628_dsi_get_lane_rate()
825 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; in rk628_dsi_get_lane_rate()
837 const struct rk628_dsi *dsi) in testif_testclk_assert() argument
839 rk628_i2c_update_bits(rk628, dsi->id ? in testif_testclk_assert()
846 const struct rk628_dsi *dsi) in testif_testclk_deassert() argument
848 rk628_i2c_update_bits(rk628, dsi->id ? in testif_testclk_deassert()
855 const struct rk628_dsi *dsi) in testif_testclr_assert() argument
857 rk628_i2c_update_bits(rk628, dsi->id ? in testif_testclr_assert()
864 const struct rk628_dsi *dsi) in testif_testclr_deassert() argument
866 rk628_i2c_update_bits(rk628, dsi->id ? in testif_testclr_deassert()
873 const struct rk628_dsi *dsi, u8 data) in testif_set_data() argument
875 rk628_i2c_update_bits(rk628, dsi->id ? in testif_set_data()
882 const struct rk628_dsi *dsi) in testif_testen_assert() argument
884 rk628_i2c_update_bits(rk628, dsi->id ? in testif_testen_assert()
891 const struct rk628_dsi *dsi) in testif_testen_deassert() argument
893 rk628_i2c_update_bits(rk628, dsi->id ? in testif_testen_deassert()
900 const struct rk628_dsi *dsi, u8 test_code) in testif_test_code_write() argument
902 testif_testclk_assert(rk628, dsi); in testif_test_code_write()
903 testif_set_data(rk628, dsi, test_code); in testif_test_code_write()
904 testif_testen_assert(rk628, dsi); in testif_test_code_write()
905 testif_testclk_deassert(rk628, dsi); in testif_test_code_write()
906 testif_testen_deassert(rk628, dsi); in testif_test_code_write()
910 const struct rk628_dsi *dsi, u8 test_data) in testif_test_data_write() argument
912 testif_testclk_deassert(rk628, dsi); in testif_test_data_write()
913 testif_set_data(rk628, dsi, test_data); in testif_test_data_write()
914 testif_testclk_assert(rk628, dsi); in testif_test_data_write()
917 static u8 testif_get_data(struct rk628 *rk628, const struct rk628_dsi *dsi) in testif_get_data() argument
921 rk628_i2c_read(rk628, dsi->id ? GRF_DPHY1_STATUS : GRF_DPHY0_STATUS, &data); in testif_get_data()
926 static void testif_write(struct rk628 *rk628, const struct rk628_dsi *dsi, in testif_write() argument
931 testif_test_code_write(rk628, dsi, reg); in testif_write()
932 testif_test_data_write(rk628, dsi, value); in testif_write()
933 monitor_data = testif_get_data(rk628, dsi); in testif_write()
937 static void testif_set_timing(const struct rk628_dsi *dsi, u8 addr, in testif_set_timing() argument
940 struct rk628 *rk628 = dsi->rk628; in testif_set_timing()
945 testif_write(rk628, dsi, addr, (max + 1) | val); in testif_set_timing()
948 static void mipi_dphy_set_timing(const struct rk628_dsi *dsi) in mipi_dphy_set_timing() argument
971 if (dsi->lane_mbps < timing_table[0].min_lane_mbps) in mipi_dphy_set_timing()
975 if (dsi->lane_mbps >= timing_table[index].min_lane_mbps && in mipi_dphy_set_timing()
976 dsi->lane_mbps < timing_table[index].max_lane_mbps) in mipi_dphy_set_timing()
982 if (dsi->lane_mbps < timing_table[index].max_lane_mbps) in mipi_dphy_set_timing()
985 testif_set_timing(dsi, 0x60, 0x3f, timing_table[index].clk_lp); in mipi_dphy_set_timing()
986 testif_set_timing(dsi, 0x61, 0x7f, timing_table[index].clk_hs_prepare); in mipi_dphy_set_timing()
987 testif_set_timing(dsi, 0x62, 0x3f, timing_table[index].clk_hs_zero); in mipi_dphy_set_timing()
988 testif_set_timing(dsi, 0x63, 0x7f, timing_table[index].clk_hs_trail); in mipi_dphy_set_timing()
989 testif_set_timing(dsi, 0x65, 0x0f, timing_table[index].clk_post); in mipi_dphy_set_timing()
990 testif_set_timing(dsi, 0x70, 0x3f, timing_table[index].data_lp); in mipi_dphy_set_timing()
991 testif_set_timing(dsi, 0x71, 0x7f, timing_table[index].data_hs_prepare); in mipi_dphy_set_timing()
992 testif_set_timing(dsi, 0x72, 0x3f, timing_table[index].data_hs_zero); in mipi_dphy_set_timing()
993 testif_set_timing(dsi, 0x73, 0x7f, timing_table[index].data_hs_trail); in mipi_dphy_set_timing()
996 static void mipi_dphy_init(struct rk628 *rk628, const struct rk628_dsi *dsi) in mipi_dphy_init() argument
1017 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) in mipi_dphy_init()
1024 testif_write(rk628, dsi, 0x44, HSFREQRANGE(hsfreqrange)); in mipi_dphy_init()
1027 mipi_dphy_set_timing(dsi); in mipi_dphy_init()
1030 static void mipi_dphy_power_on(struct rk628 *rk628, const struct rk628_dsi *dsi) in mipi_dphy_power_on() argument
1036 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in mipi_dphy_power_on()
1038 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); in mipi_dphy_power_on()
1039 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); in mipi_dphy_power_on()
1040 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); in mipi_dphy_power_on()
1041 testif_testclr_assert(rk628, dsi); in mipi_dphy_power_on()
1044 rk628_i2c_update_bits(rk628, dsi->id ? in mipi_dphy_power_on()
1050 testif_testclr_deassert(rk628, dsi); in mipi_dphy_power_on()
1052 mipi_dphy_init(rk628, dsi); in mipi_dphy_power_on()
1054 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, in mipi_dphy_power_on()
1056 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, in mipi_dphy_power_on()
1058 dsi_update_bits(rk628, dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); in mipi_dphy_power_on()
1101 const struct rk628_dsi *dsi) in rk628_dsi_bridge_pre_enable() argument
1105 dsi_write(rk628, dsi, DSI_PWR_UP, RESET); in rk628_dsi_bridge_pre_enable()
1106 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_COMMAND_MODE)); in rk628_dsi_bridge_pre_enable()
1108 val = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); in rk628_dsi_bridge_pre_enable()
1109 dsi_write(rk628, dsi, DSI_CLKMGR_CFG, in rk628_dsi_bridge_pre_enable()
1113 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_EOT_PACKET) in rk628_dsi_bridge_pre_enable()
1116 dsi_write(rk628, dsi, DSI_PCKHDL_CFG, val); in rk628_dsi_bridge_pre_enable()
1118 dsi_write(rk628, dsi, DSI_TO_CNT_CFG, in rk628_dsi_bridge_pre_enable()
1120 dsi_write(rk628, dsi, DSI_BTA_TO_CNT, 0xd00); in rk628_dsi_bridge_pre_enable()
1121 dsi_write(rk628, dsi, DSI_PHY_TMR_CFG, in rk628_dsi_bridge_pre_enable()
1124 dsi_write(rk628, dsi, DSI_PHY_TMR_LPCLK_CFG, in rk628_dsi_bridge_pre_enable()
1126 dsi_write(rk628, dsi, DSI_PHY_IF_CFG, in rk628_dsi_bridge_pre_enable()
1127 PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes - 1)); in rk628_dsi_bridge_pre_enable()
1129 mipi_dphy_power_on(rk628, dsi); in rk628_dsi_bridge_pre_enable()
1131 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP); in rk628_dsi_bridge_pre_enable()
1135 const struct rk628_dsi *dsi, in rk628_dsi_set_vid_mode() argument
1138 unsigned int lanebyteclk = (dsi->lane_mbps * 1000L) >> 3; in rk628_dsi_set_vid_mode()
1148 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_HFP) in rk628_dsi_set_vid_mode()
1151 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_HBP) in rk628_dsi_set_vid_mode()
1154 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_BURST) in rk628_dsi_set_vid_mode()
1156 else if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in rk628_dsi_set_vid_mode()
1161 dsi_write(rk628, dsi, DSI_VID_MODE_CFG, val); in rk628_dsi_set_vid_mode()
1163 if (dsi->mode_flags & RK628_MIPI_DSI_CLOCK_NON_CONTINUOUS) in rk628_dsi_set_vid_mode()
1164 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL, in rk628_dsi_set_vid_mode()
1167 if (dsi->slave || dsi->master) in rk628_dsi_set_vid_mode()
1172 dsi_write(rk628, dsi, DSI_VID_PKT_SIZE, pkt_size); in rk628_dsi_set_vid_mode()
1184 dsi_write(rk628, dsi, DSI_VID_HLINE_TIME, in rk628_dsi_set_vid_mode()
1188 dsi_write(rk628, dsi, DSI_VID_HSA_TIME, VID_HSA_TIME(hsa_time)); in rk628_dsi_set_vid_mode()
1191 dsi_write(rk628, dsi, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time)); in rk628_dsi_set_vid_mode()
1193 dsi_write(rk628, dsi, DSI_VID_VACTIVE_LINES, vactive); in rk628_dsi_set_vid_mode()
1194 dsi_write(rk628, dsi, DSI_VID_VSA_LINES, vsa); in rk628_dsi_set_vid_mode()
1195 dsi_write(rk628, dsi, DSI_VID_VFP_LINES, vfp); in rk628_dsi_set_vid_mode()
1196 dsi_write(rk628, dsi, DSI_VID_VBP_LINES, vbp); in rk628_dsi_set_vid_mode()
1198 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_VIDEO_MODE)); in rk628_dsi_set_vid_mode()
1202 const struct rk628_dsi *dsi, in rk628_dsi_set_cmd_mode() argument
1207 dsi_update_bits(rk628, dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); in rk628_dsi_set_cmd_mode()
1215 dsi_write(rk628, dsi, DSI_EDPI_CMD_SIZE, cmd_size); in rk628_dsi_set_cmd_mode()
1217 if (dsi->mode_flags & RK628_MIPI_DSI_CLOCK_NON_CONTINUOUS) in rk628_dsi_set_cmd_mode()
1218 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL, in rk628_dsi_set_cmd_mode()
1221 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_COMMAND_MODE)); in rk628_dsi_set_cmd_mode()
1225 const struct rk628_dsi *dsi) in rk628_dsi_bridge_enable() argument
1230 dsi_write(rk628, dsi, DSI_PWR_UP, RESET); in rk628_dsi_bridge_enable()
1232 switch (dsi->bus_format) { in rk628_dsi_bridge_enable()
1249 dsi_write(rk628, dsi, DSI_DPI_COLOR_CODING, val); in rk628_dsi_bridge_enable()
1257 dsi_write(rk628, dsi, DSI_DPI_CFG_POL, val); in rk628_dsi_bridge_enable()
1259 dsi_write(rk628, dsi, DSI_DPI_VCID, DPI_VID(0)); in rk628_dsi_bridge_enable()
1260 dsi_write(rk628, dsi, DSI_DPI_LP_CMD_TIM, in rk628_dsi_bridge_enable()
1262 dsi_update_bits(rk628, dsi, DSI_LPCLK_CTRL, in rk628_dsi_bridge_enable()
1265 if (dsi->mode_flags & RK628_MIPI_DSI_MODE_VIDEO) in rk628_dsi_bridge_enable()
1266 rk628_dsi_set_vid_mode(rk628, dsi, mode); in rk628_dsi_bridge_enable()
1268 rk628_dsi_set_cmd_mode(rk628, dsi, mode); in rk628_dsi_bridge_enable()
1270 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP); in rk628_dsi_bridge_enable()
1275 struct rk628_dsi *dsi = &rk628->dsi0; in rk628_mipi_dsi_pre_enable() local
1277 u32 rate = rk628_dsi_get_lane_rate(dsi); in rk628_mipi_dsi_pre_enable()
1289 (dsi->slave ? GRF_DPHY_CH1_EN(1) : 0) | in rk628_mipi_dsi_pre_enable()
1295 dsi->slave ? SW_SPLIT_EN : 0); in rk628_mipi_dsi_pre_enable()
1298 if (dsi->slave) in rk628_mipi_dsi_pre_enable()
1300 else if (dsi->id) in rk628_mipi_dsi_pre_enable()
1307 dsi->lane_mbps = rk628_combtxphy_get_bus_width(rk628); in rk628_mipi_dsi_pre_enable()
1309 if (dsi->slave && dsi1) in rk628_mipi_dsi_pre_enable()
1318 rk628_dsi_bridge_pre_enable(rk628, dsi); in rk628_mipi_dsi_pre_enable()
1320 if (dsi->slave) { in rk628_mipi_dsi_pre_enable()
1343 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); in rk628_mipi_dsi_pre_enable()
1348 const struct rk628_dsi *dsi = &rk628->dsi0; in rk628_mipi_dsi_enable() local
1351 rk628_dsi_bridge_enable(rk628, dsi); in rk628_mipi_dsi_enable()
1353 if (dsi->slave) in rk628_mipi_dsi_enable()
1361 const struct rk628_dsi *dsi = &rk628->dsi0; in rk628_dsi_disable() local
1366 dsi_write(rk628, dsi, DSI_PWR_UP, RESET); in rk628_dsi_disable()
1367 dsi_write(rk628, dsi, DSI_LPCLK_CTRL, 0); in rk628_dsi_disable()
1368 dsi_write(rk628, dsi, DSI_EDPI_CMD_SIZE, 0); in rk628_dsi_disable()
1369 dsi_write(rk628, dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(RK628_DSI_COMMAND_MODE)); in rk628_dsi_disable()
1370 dsi_write(rk628, dsi, DSI_PWR_UP, POWER_UP); in rk628_dsi_disable()
1374 if (dsi->slave) { in rk628_dsi_disable()