Lines Matching refs:inno
334 static inline void phy_update_bits(struct inno_video_phy *inno, in phy_update_bits() argument
340 orig = readl(inno->phy.start + reg); in phy_update_bits()
343 writel(tmp, inno->phy.start + reg); in phy_update_bits()
346 static inline void host_update_bits(struct inno_video_phy *inno, in host_update_bits() argument
351 orig = readl(inno->host.start + reg); in host_update_bits()
354 writel(tmp, inno->host.start + reg); in host_update_bits()
386 inno_mipi_dphy_get_timing(struct inno_video_phy *inno) in inno_mipi_dphy_get_timing() argument
390 unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC; in inno_mipi_dphy_get_timing()
393 timings = inno->mipi_dphy_info->inno_mipi_dphy_timing_table; in inno_mipi_dphy_get_timing()
394 num_timings = inno->mipi_dphy_info->num_timings; in inno_mipi_dphy_get_timing()
406 static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy *inno) in inno_mipi_dphy_max_2_5GHz_pll_enable() argument
408 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
409 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
410 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
411 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
412 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_2_5GHz_pll_enable()
413 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
414 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_mipi_dphy_max_2_5GHz_pll_enable()
416 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, in inno_mipi_dphy_max_2_5GHz_pll_enable()
419 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_2_5GHz_pll_enable()
424 static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy *inno) in inno_mipi_dphy_max_1GHz_pll_enable() argument
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
428 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_max_1GHz_pll_enable()
429 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
430 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_max_1GHz_pll_enable()
431 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_1GHz_pll_enable()
432 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_1GHz_pll_enable()
434 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_1GHz_pll_enable()
439 static void inno_mipi_dphy_reset(struct inno_video_phy *inno) in inno_mipi_dphy_reset() argument
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
445 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
448 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_mipi_dphy_reset()
451 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_mipi_dphy_reset()
455 static void inno_mipi_dphy_timing_init(struct inno_video_phy *inno) in inno_mipi_dphy_timing_init() argument
465 txbyteclkhs = inno->pll.rate / 8; in inno_mipi_dphy_timing_init()
471 ui = div_u64(PSEC_PER_SEC, inno->pll.rate); in inno_mipi_dphy_timing_init()
519 timing = inno_mipi_dphy_get_timing(inno); in inno_mipi_dphy_timing_init()
525 if (inno->mipi_dphy_info->phy_max_rate == MAX_1GHZ) { in inno_mipi_dphy_timing_init()
545 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, in inno_mipi_dphy_timing_init()
547 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, in inno_mipi_dphy_timing_init()
550 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) in inno_mipi_dphy_timing_init()
551 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK, in inno_mipi_dphy_timing_init()
554 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
556 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, in inno_mipi_dphy_timing_init()
559 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) in inno_mipi_dphy_timing_init()
560 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK, in inno_mipi_dphy_timing_init()
563 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
566 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) in inno_mipi_dphy_timing_init()
567 phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK, in inno_mipi_dphy_timing_init()
570 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
572 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, in inno_mipi_dphy_timing_init()
574 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, in inno_mipi_dphy_timing_init()
576 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, in inno_mipi_dphy_timing_init()
578 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, in inno_mipi_dphy_timing_init()
580 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, in inno_mipi_dphy_timing_init()
582 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, in inno_mipi_dphy_timing_init()
587 static void inno_mipi_dphy_lane_enable(struct inno_video_phy *inno) in inno_mipi_dphy_lane_enable() argument
591 switch (inno->lanes) { in inno_mipi_dphy_lane_enable()
607 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val); in inno_mipi_dphy_lane_enable()
610 static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno) in inno_video_phy_mipi_mode_enable() argument
613 (struct rockchip_phy *)dev_get_driver_data(inno->dev); in inno_video_phy_mipi_mode_enable()
616 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_video_phy_mipi_mode_enable()
621 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01, in inno_video_phy_mipi_mode_enable()
624 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) in inno_video_phy_mipi_mode_enable()
625 inno_mipi_dphy_max_2_5GHz_pll_enable(inno); in inno_video_phy_mipi_mode_enable()
627 inno_mipi_dphy_max_1GHz_pll_enable(inno); in inno_video_phy_mipi_mode_enable()
629 inno_mipi_dphy_reset(inno); in inno_video_phy_mipi_mode_enable()
630 inno_mipi_dphy_timing_init(inno); in inno_video_phy_mipi_mode_enable()
631 inno_mipi_dphy_lane_enable(inno); in inno_video_phy_mipi_mode_enable()
634 static void inno_dsiphy_lvds_voltage_set(struct inno_video_phy *inno) in inno_dsiphy_lvds_voltage_set() argument
639 if (inno->mipi_dphy_info->phy_max_rate == MAX_1GHZ) in inno_dsiphy_lvds_voltage_set()
642 if (inno->lvds_vcom >= 1000) in inno_dsiphy_lvds_voltage_set()
644 else if (inno->lvds_vcom >= 950) in inno_dsiphy_lvds_voltage_set()
646 else if (inno->lvds_vcom >= 900) in inno_dsiphy_lvds_voltage_set()
651 if (inno->lvds_vod >= 400) in inno_dsiphy_lvds_voltage_set()
653 else if (inno->lvds_vod >= 350) in inno_dsiphy_lvds_voltage_set()
655 else if (inno->lvds_vod >= 300) in inno_dsiphy_lvds_voltage_set()
660 phy_update_bits(inno, REGISTER_PART_LVDS, 0x04, LVDS_VCOM_MASK | LVDS_VOD_MASK, val); in inno_dsiphy_lvds_voltage_set()
663 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno) in inno_video_phy_lvds_mode_enable() argument
671 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_video_phy_lvds_mode_enable()
677 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_video_phy_lvds_mode_enable()
680 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_video_phy_lvds_mode_enable()
683 inno_dsiphy_lvds_voltage_set(inno); in inno_video_phy_lvds_mode_enable()
685 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_video_phy_lvds_mode_enable()
689 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_video_phy_lvds_mode_enable()
691 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_video_phy_lvds_mode_enable()
693 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_video_phy_lvds_mode_enable()
695 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); in inno_video_phy_lvds_mode_enable()
698 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_video_phy_lvds_mode_enable()
702 ret = readl_poll_timeout(inno->host.start + DSI_PHY_STATUS, in inno_video_phy_lvds_mode_enable()
708 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e, in inno_video_phy_lvds_mode_enable()
712 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_video_phy_lvds_mode_enable()
716 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_video_phy_lvds_mode_enable()
722 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno) in inno_video_phy_ttl_mode_enable() argument
725 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_video_phy_ttl_mode_enable()
728 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, in inno_video_phy_ttl_mode_enable()
733 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_video_phy_ttl_mode_enable()
736 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_video_phy_ttl_mode_enable()
740 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_video_phy_ttl_mode_enable()
745 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); in inno_video_phy_ttl_mode_enable()
750 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_power_on() local
753 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_video_phy_power_on()
756 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_video_phy_power_on()
759 switch (inno->mode) { in inno_video_phy_power_on()
761 inno_video_phy_mipi_mode_enable(inno); in inno_video_phy_power_on()
764 inno_video_phy_lvds_mode_enable(inno); in inno_video_phy_power_on()
767 inno_video_phy_ttl_mode_enable(inno); in inno_video_phy_power_on()
778 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_power_off() local
780 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); in inno_video_phy_power_off()
781 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_video_phy_power_off()
784 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_video_phy_power_off()
786 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_video_phy_power_off()
789 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); in inno_video_phy_power_off()
790 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, in inno_video_phy_power_off()
793 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, in inno_video_phy_power_off()
872 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_set_pll() local
883 inno->pll.prediv = prediv; in inno_video_phy_set_pll()
884 inno->pll.fbdiv = fbdiv; in inno_video_phy_set_pll()
885 inno->pll.rate = fout; in inno_video_phy_set_pll()
893 struct inno_video_phy *inno = dev_get_priv(phy->dev); in inno_video_phy_set_mode() local
899 inno->mode = mode; in inno_video_phy_set_mode()
910 struct inno_video_phy *inno = dev_get_priv(dev); in inno_video_phy_probe() local
923 inno->dev = dev; in inno_video_phy_probe()
924 inno->mipi_dphy_info = phy->data; in inno_video_phy_probe()
926 inno->mipi_dphy_info = &inno_video_mipi_dphy_max_2_5GHz; in inno_video_phy_probe()
928 inno->lanes = ofnode_read_u32_default(dev->node, "inno,lanes", 4); in inno_video_phy_probe()
929 inno->lvds_vcom = ofnode_read_u32_default(dev->node, "inno,lvds-vcom", 950); in inno_video_phy_probe()
930 inno->lvds_vod = ofnode_read_u32_default(dev->node, "inno,lvds-vod", 350); in inno_video_phy_probe()
932 ret = dev_read_resource(dev, 0, &inno->phy); in inno_video_phy_probe()
938 ret = dev_read_resource(dev, 1, &inno->host); in inno_video_phy_probe()