391 	unsigned int i;  in inno_mipi_dphy_get_timing()  local
396 	for (i = 0; i < num_timings; i++)  in inno_mipi_dphy_get_timing()
397 		if (lane_mbps <= timings[i].max_lane_mbps)  in inno_mipi_dphy_get_timing()
400 	if (i == num_timings)  in inno_mipi_dphy_get_timing()
401 		--i;  in inno_mipi_dphy_get_timing()
403 	return &timings[i];  in inno_mipi_dphy_get_timing()
463 	unsigned int i;  in inno_mipi_dphy_timing_init()  local
539 	for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {  in inno_mipi_dphy_timing_init()
540 		if (i == REGISTER_PART_CLOCK_LANE)  in inno_mipi_dphy_timing_init()
545 		phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,  in inno_mipi_dphy_timing_init()
547 		phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,  in inno_mipi_dphy_timing_init()
551 			phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,  in inno_mipi_dphy_timing_init()
554 		phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
556 		phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,  in inno_mipi_dphy_timing_init()
560 			phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,  in inno_mipi_dphy_timing_init()
563 		phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
567 			phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,  in inno_mipi_dphy_timing_init()
570 		phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
572 		phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,  in inno_mipi_dphy_timing_init()
574 		phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,  in inno_mipi_dphy_timing_init()
576 		phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
578 		phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,  in inno_mipi_dphy_timing_init()
580 		phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,  in inno_mipi_dphy_timing_init()
582 		phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,  in inno_mipi_dphy_timing_init()