295 static inline void inno_update_bits(struct inno_mipi_dphy *inno, u32 reg,  in inno_update_bits()  function
343 	inno_update_bits(inno, base + T_HS_PREPARE_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
347 	inno_update_bits(inno, base + T_HS_ZERO_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
351 	inno_update_bits(inno, base + T_HS_TRAIL_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
355 	inno_update_bits(inno, base + T_HS_EXIT_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
360 		inno_update_bits(inno, base + T_CLK_POST_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
363 		inno_update_bits(inno, base + T_CLK_POST_OFFSET_H, m, v);  in inno_mipi_dphy_timing_update()
366 		inno_update_bits(inno, base + T_CLK_PRE_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
371 	inno_update_bits(inno, base + T_WAKUP_H_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
375 	inno_update_bits(inno, base + T_WAKUP_L_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
379 	inno_update_bits(inno, base + T_LPX_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
383 	inno_update_bits(inno, base + T_TA_GO_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
387 	inno_update_bits(inno, base + T_TA_SURE_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
391 	inno_update_bits(inno, base + T_TA_WAIT_OFFSET, m, v);  in inno_mipi_dphy_timing_update()
543 	inno_update_bits(inno, INNO_PHY_POWER_CTRL,  in inno_mipi_dphy_reset()
546 	inno_update_bits(inno, INNO_PHY_POWER_CTRL,  in inno_mipi_dphy_reset()
549 	inno_update_bits(inno, INNO_PHY_DIG_CTRL,  in inno_mipi_dphy_reset()
552 	inno_update_bits(inno, INNO_PHY_DIG_CTRL,  in inno_mipi_dphy_reset()
600 	inno_update_bits(inno, INNO_PHY_LANE_CTRL, m, v);  in inno_mipi_dphy_lane_enable()
605 	inno_update_bits(inno, INNO_PHY_POWER_CTRL,  in inno_mipi_dphy_pll_ldo_disable()
612 	inno_update_bits(inno, INNO_PHY_POWER_CTRL,  in inno_mipi_dphy_pll_ldo_enable()
619 	inno_update_bits(inno, INNO_PHY_LANE_CTRL, PWROK_BP | PWROK, PWROK);  in inno_mipi_dphy_da_pwrok_enable()
624 	inno_update_bits(inno, INNO_PHY_LANE_CTRL, PWROK_BP | PWROK, PWROK_BP);  in inno_mipi_dphy_da_pwrok_disable()
629 	inno_update_bits(inno, INNO_PHY_LANE_CTRL, MIPI_BGPD, 0);  in inno_mipi_dphy_bgpd_enable()
634 	inno_update_bits(inno, INNO_PHY_LANE_CTRL, MIPI_BGPD, MIPI_BGPD);  in inno_mipi_dphy_bgpd_disable()
635 	inno_update_bits(inno, INNO_PHY_LVDS_CTRL, LVDS_BGPD, LVDS_BGPD);  in inno_mipi_dphy_bgpd_disable()
655 	inno_update_bits(inno, INNO_PHY_LANE_CTRL, 0x7c, 0x00);  in inno_mipi_dphy_lane_disable()
687 	inno_update_bits(inno, INNO_PHY_PLL_CTRL_0, m, v);  in inno_mipi_dphy_set_pll()
691 	inno_update_bits(inno, INNO_PHY_PLL_CTRL_1, m, v);  in inno_mipi_dphy_set_pll()
694 		inno_update_bits(inno, ANALOG_REG_08,  in inno_mipi_dphy_set_pll()
696 		inno_update_bits(inno, ANALOG_REG_0B,  in inno_mipi_dphy_set_pll()
702 		inno_update_bits(inno, RK3506_PRE_EMPHASIS,  in inno_mipi_dphy_set_pll()
704 		inno_update_bits(inno, RK3506_PRE_EMPHASIS,  in inno_mipi_dphy_set_pll()
706 		inno_update_bits(inno, PRE_EMPHASIS_RANGE,  in inno_mipi_dphy_set_pll()
709 		inno_update_bits(inno, LANE0_PRE_EMPHASIS_RANGE,  in inno_mipi_dphy_set_pll()
712 		inno_update_bits(inno, LANE1_PRE_EMPHASIS_RANGE,  in inno_mipi_dphy_set_pll()
715 		inno_update_bits(inno, ANALOG_REG_0B,  in inno_mipi_dphy_set_pll()