256 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)  in dsi_write()  argument
258 	writel(val, dsi->base + reg);  in dsi_write()
261 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)  in dsi_read()  argument
263 	return readl(dsi->base + reg);  in dsi_read()
266 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi,  in dsi_update_bits()  argument
271 	orig = dsi_read(dsi, reg);  in dsi_update_bits()
274 	dsi_write(dsi, reg, tmp);  in dsi_update_bits()
277 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index,  in grf_field_write()  argument
280 	const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] :  in grf_field_write()
281 			  dsi->pdata->dsi0_grf_reg_fields[index];  in grf_field_write()
292 	rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb);  in grf_field_write()
295 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi)  in dpishutdn_assert()  argument
297 	grf_field_write(dsi, DPISHUTDN, 1);  in dpishutdn_assert()
300 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi)  in dpishutdn_deassert()  argument
302 	grf_field_write(dsi, DPISHUTDN, 0);  in dpishutdn_deassert()
305 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)  in genif_wait_w_pld_fifo_not_full()  argument
310 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in genif_wait_w_pld_fifo_not_full()
321 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)  in genif_wait_cmd_fifo_not_full()  argument
326 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in genif_wait_cmd_fifo_not_full()
337 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)  in genif_wait_write_fifo_empty()  argument
344 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in genif_wait_write_fifo_empty()
355 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi)  in mipi_dphy_enableclk_assert()  argument
357 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);  in mipi_dphy_enableclk_assert()
361 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi)  in mipi_dphy_enableclk_deassert()  argument
363 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);  in mipi_dphy_enableclk_deassert()
367 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi)  in mipi_dphy_shutdownz_assert()  argument
369 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);  in mipi_dphy_shutdownz_assert()
373 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi)  in mipi_dphy_shutdownz_deassert()  argument
375 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);  in mipi_dphy_shutdownz_deassert()
379 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi)  in mipi_dphy_rstz_assert()  argument
381 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0);  in mipi_dphy_rstz_assert()
385 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi)  in mipi_dphy_rstz_deassert()  argument
387 	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);  in mipi_dphy_rstz_deassert()
391 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi)  in testif_testclk_assert()  argument
393 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);  in testif_testclk_assert()
397 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi)  in testif_testclk_deassert()  argument
399 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0);  in testif_testclk_deassert()
403 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi)  in testif_testclr_assert()  argument
405 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR);  in testif_testclr_assert()
409 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi)  in testif_testclr_deassert()  argument
411 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0);  in testif_testclr_deassert()
415 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi)  in testif_testen_assert()  argument
417 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);  in testif_testen_assert()
421 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi)  in testif_testen_deassert()  argument
423 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0);  in testif_testen_deassert()
427 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data)  in testif_set_data()  argument
429 	dsi_update_bits(dsi, DSI_PHY_TST_CTRL1,  in testif_set_data()
434 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi)  in testif_get_data()  argument
436 	return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT;  in testif_get_data()
439 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code)  in testif_test_code_write()  argument
441 	testif_testclk_assert(dsi);  in testif_test_code_write()
442 	testif_set_data(dsi, test_code);  in testif_test_code_write()
443 	testif_testen_assert(dsi);  in testif_test_code_write()
444 	testif_testclk_deassert(dsi);  in testif_test_code_write()
445 	testif_testen_deassert(dsi);  in testif_test_code_write()
448 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data)  in testif_test_data_write()  argument
450 	testif_testclk_deassert(dsi);  in testif_test_data_write()
451 	testif_set_data(dsi, test_data);  in testif_test_data_write()
452 	testif_testclk_assert(dsi);  in testif_test_data_write()
455 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data)  in testif_write()  argument
457 	testif_test_code_write(dsi, test_code);  in testif_write()
458 	testif_test_data_write(dsi, test_data);  in testif_write()
460 	dev_dbg(dsi->dev,  in testif_write()
462 		test_code, test_data, testif_get_data(dsi));  in testif_write()
465 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)  in mipi_dphy_power_on()  argument
470 	mipi_dphy_shutdownz_deassert(dsi);  in mipi_dphy_power_on()
471 	mipi_dphy_rstz_deassert(dsi);  in mipi_dphy_power_on()
474 	if (dsi->dphy.phy) {  in mipi_dphy_power_on()
475 		rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_MIPI_DPHY);  in mipi_dphy_power_on()
476 		rockchip_phy_power_on(dsi->dphy.phy);  in mipi_dphy_power_on()
479 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,  in mipi_dphy_power_on()
482 		dev_err(dsi->dev, "PHY is not locked\n");  in mipi_dphy_power_on()
489 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,  in mipi_dphy_power_on()
493 		dev_err(dsi->dev, "lane module is not in stop state\n");  in mipi_dphy_power_on()
502 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_phy_init()  argument
525 		if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)  in dw_mipi_dsi_phy_init()
532 	testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange));  in dw_mipi_dsi_phy_init()
534 	txbyteclkhs = dsi->lane_mbps >> 3;  in dw_mipi_dsi_phy_init()
536 	testif_write(dsi, 0x60, 0x80 | counter);  in dw_mipi_dsi_phy_init()
537 	testif_write(dsi, 0x70, 0x80 | counter);  in dw_mipi_dsi_phy_init()
539 	n = dsi->dphy.input_div - 1;  in dw_mipi_dsi_phy_init()
540 	m = dsi->dphy.feedback_div - 1;  in dw_mipi_dsi_phy_init()
541 	testif_write(dsi, 0x19, 0x30);  in dw_mipi_dsi_phy_init()
542 	testif_write(dsi, 0x17, INPUT_DIV(n));  in dw_mipi_dsi_phy_init()
543 	testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m));  in dw_mipi_dsi_phy_init()
544 	testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5));  in dw_mipi_dsi_phy_init()
547 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_get_lane_rate()  argument
549 	const struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_get_lane_rate()
550 	unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane;  in dw_mipi_dsi_get_lane_rate()
557 	value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0);  in dw_mipi_dsi_get_lane_rate()
561 	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);  in dw_mipi_dsi_get_lane_rate()
565 	lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;  in dw_mipi_dsi_get_lane_rate()
581 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate)  in dw_mipi_dsi_set_pll()  argument
639 	dsi->lane_mbps = best_freq / 1000 / 1000;  in dw_mipi_dsi_set_pll()
640 	dsi->dphy.input_div = best_prediv;  in dw_mipi_dsi_set_pll()
641 	dsi->dphy.feedback_div = best_fbdiv;  in dw_mipi_dsi_set_pll()
642 	if (dsi->slave) {  in dw_mipi_dsi_set_pll()
643 		dsi->slave->lane_mbps = dsi->lane_mbps;  in dw_mipi_dsi_set_pll()
644 		dsi->slave->dphy.input_div = dsi->dphy.input_div;  in dw_mipi_dsi_set_pll()
645 		dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div;  in dw_mipi_dsi_set_pll()
647 	if (dsi->master) {  in dw_mipi_dsi_set_pll()
648 		dsi->master->lane_mbps = dsi->lane_mbps;  in dw_mipi_dsi_set_pll()
649 		dsi->master->dphy.input_div = dsi->dphy.input_div;  in dw_mipi_dsi_set_pll()
650 		dsi->master->dphy.feedback_div = dsi->dphy.feedback_div;  in dw_mipi_dsi_set_pll()
654 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_read_from_fifo()  argument
662 	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_read_from_fifo()
671 		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,  in dw_mipi_dsi_read_from_fifo()
678 		val = dsi_read(dsi, DSI_GEN_PLD_DATA);  in dw_mipi_dsi_read_from_fifo()
702 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_turn_on_peripheral()  argument
704 	dpishutdn_assert(dsi);  in dw_mipi_dsi_turn_on_peripheral()
706 	dpishutdn_deassert(dsi);  in dw_mipi_dsi_turn_on_peripheral()
711 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_shutdown_peripheral()  argument
713 	dpishutdn_deassert(dsi);  in dw_mipi_dsi_shutdown_peripheral()
715 	dpishutdn_assert(dsi);  in dw_mipi_dsi_shutdown_peripheral()
720 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_transfer()  argument
728 		dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN);  in dw_mipi_dsi_transfer()
729 		dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0);  in dw_mipi_dsi_transfer()
731 		dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0);  in dw_mipi_dsi_transfer()
732 		dsi_update_bits(dsi, DSI_LPCLK_CTRL,  in dw_mipi_dsi_transfer()
738 		return dw_mipi_dsi_shutdown_peripheral(dsi);  in dw_mipi_dsi_transfer()
740 		return dw_mipi_dsi_turn_on_peripheral(dsi);  in dw_mipi_dsi_transfer()
742 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,  in dw_mipi_dsi_transfer()
743 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
747 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,  in dw_mipi_dsi_transfer()
748 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
752 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX,  in dw_mipi_dsi_transfer()
753 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
757 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,  in dw_mipi_dsi_transfer()
758 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
762 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE,  in dw_mipi_dsi_transfer()
763 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
767 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,  in dw_mipi_dsi_transfer()
768 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
772 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,  in dw_mipi_dsi_transfer()
773 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
777 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,  in dw_mipi_dsi_transfer()
778 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
782 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX,  in dw_mipi_dsi_transfer()
783 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
787 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,  in dw_mipi_dsi_transfer()
788 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
792 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,  in dw_mipi_dsi_transfer()
793 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
797 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,  in dw_mipi_dsi_transfer()
798 				dsi->mode_flags & MIPI_DSI_MODE_LPM ?  in dw_mipi_dsi_transfer()
806 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG,  in dw_mipi_dsi_transfer()
827 		ret = genif_wait_w_pld_fifo_not_full(dsi);  in dw_mipi_dsi_transfer()
835 			dsi_write(dsi, DSI_GEN_PLD_DATA, val);  in dw_mipi_dsi_transfer()
839 			dsi_write(dsi, DSI_GEN_PLD_DATA, val);  in dw_mipi_dsi_transfer()
845 	ret = genif_wait_cmd_fifo_not_full(dsi);  in dw_mipi_dsi_transfer()
851 	dsi_write(dsi, DSI_GEN_HDR, val);  in dw_mipi_dsi_transfer()
853 	ret = genif_wait_write_fifo_empty(dsi);  in dw_mipi_dsi_transfer()
858 		ret = dw_mipi_dsi_read_from_fifo(dsi, msg);  in dw_mipi_dsi_transfer()
863 	if (dsi->slave) {  in dw_mipi_dsi_transfer()
864 		ret = dw_mipi_dsi_transfer(dsi->slave, msg);  in dw_mipi_dsi_transfer()
872 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_video_mode_config()  argument
877 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)  in dw_mipi_dsi_video_mode_config()
880 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)  in dw_mipi_dsi_video_mode_config()
883 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)  in dw_mipi_dsi_video_mode_config()
885 	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)  in dw_mipi_dsi_video_mode_config()
890 	dsi_write(dsi, DSI_VID_MODE_CFG, val);  in dw_mipi_dsi_video_mode_config()
892 	if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)  in dw_mipi_dsi_video_mode_config()
893 		dsi_update_bits(dsi, DSI_LPCLK_CTRL,  in dw_mipi_dsi_video_mode_config()
897 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_enable()  argument
899 	const struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_enable()
901 	dsi_update_bits(dsi, DSI_LPCLK_CTRL,  in dw_mipi_dsi_enable()
904 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_enable()
906 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {  in dw_mipi_dsi_enable()
907 		dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE);  in dw_mipi_dsi_enable()
909 		dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel));  in dw_mipi_dsi_enable()
910 		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);  in dw_mipi_dsi_enable()
911 		dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay);  in dw_mipi_dsi_enable()
912 		dsi_update_bits(dsi, DSI_MODE_CFG,  in dw_mipi_dsi_enable()
916 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_enable()
918 	if (dsi->slave)  in dw_mipi_dsi_enable()
919 		dw_mipi_dsi_enable(dsi->slave);  in dw_mipi_dsi_enable()
922 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_disable()  argument
924 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_disable()
925 	dsi_write(dsi, DSI_LPCLK_CTRL, 0);  in dw_mipi_dsi_disable()
926 	dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0);  in dw_mipi_dsi_disable()
927 	dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE);  in dw_mipi_dsi_disable()
928 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_disable()
930 	if (dsi->slave)  in dw_mipi_dsi_disable()
931 		dw_mipi_dsi_disable(dsi->slave);  in dw_mipi_dsi_disable()
934 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_post_disable()  argument
936 	if (!dsi->prepared)  in dw_mipi_dsi_post_disable()
939 	if (dsi->master)  in dw_mipi_dsi_post_disable()
940 		dw_mipi_dsi_post_disable(dsi->master);  in dw_mipi_dsi_post_disable()
942 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_post_disable()
943 	dsi_write(dsi, DSI_PHY_RSTZ, 0);  in dw_mipi_dsi_post_disable()
945 	if (dsi->dphy.phy)  in dw_mipi_dsi_post_disable()
946 		rockchip_phy_power_off(dsi->dphy.phy);  in dw_mipi_dsi_post_disable()
948 	dsi->prepared = false;  in dw_mipi_dsi_post_disable()
950 	if (dsi->slave)  in dw_mipi_dsi_post_disable()
951 		dw_mipi_dsi_post_disable(dsi->slave);  in dw_mipi_dsi_post_disable()
954 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_init()  argument
958 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_init()
961 	esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);  in dw_mipi_dsi_init()
962 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |  in dw_mipi_dsi_init()
966 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_dpi_config()  argument
971 	switch (dsi->format) {  in dw_mipi_dsi_dpi_config()
991 	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));  in dw_mipi_dsi_dpi_config()
992 	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);  in dw_mipi_dsi_dpi_config()
993 	dsi_write(dsi, DSI_DPI_CFG_POL, val);  in dw_mipi_dsi_dpi_config()
994 	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)  in dw_mipi_dsi_dpi_config()
998 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_packet_handler_config()  argument
1002 	if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)  in dw_mipi_dsi_packet_handler_config()
1005 	dsi_write(dsi, DSI_PCKHDL_CFG, val);  in dw_mipi_dsi_packet_handler_config()
1008 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_video_packet_config()  argument
1011 	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));  in dw_mipi_dsi_video_packet_config()
1014 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_command_mode_config()  argument
1016 	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));  in dw_mipi_dsi_command_mode_config()
1017 	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);  in dw_mipi_dsi_command_mode_config()
1021 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,  in dw_mipi_dsi_get_hcomponent_lbcc()  argument
1026 	lbcc = hcomponent * dsi->lane_mbps * 1000 / 8;  in dw_mipi_dsi_get_hcomponent_lbcc()
1028 	if (!dsi->mode.clock)  in dw_mipi_dsi_get_hcomponent_lbcc()
1031 	return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock);  in dw_mipi_dsi_get_hcomponent_lbcc()
1034 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_line_timer_config()  argument
1037 	struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_line_timer_config()
1043 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);  in dw_mipi_dsi_line_timer_config()
1044 	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
1046 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);  in dw_mipi_dsi_line_timer_config()
1047 	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
1049 	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);  in dw_mipi_dsi_line_timer_config()
1050 	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
1053 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_vertical_timing_config()  argument
1056 	struct drm_display_mode *mode = &dsi->mode;  in dw_mipi_dsi_vertical_timing_config()
1063 	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);  in dw_mipi_dsi_vertical_timing_config()
1064 	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);  in dw_mipi_dsi_vertical_timing_config()
1065 	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);  in dw_mipi_dsi_vertical_timing_config()
1066 	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);  in dw_mipi_dsi_vertical_timing_config()
1069 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_dphy_timing_config()  argument
1071 	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)  in dw_mipi_dsi_dphy_timing_config()
1074 	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)  in dw_mipi_dsi_dphy_timing_config()
1078 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_dphy_interface_config()  argument
1080 	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |  in dw_mipi_dsi_dphy_interface_config()
1081 		  N_LANES(dsi->lanes));  in dw_mipi_dsi_dphy_interface_config()
1084 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_clear_err()  argument
1086 	dsi_read(dsi, DSI_INT_ST0);  in dw_mipi_dsi_clear_err()
1087 	dsi_read(dsi, DSI_INT_ST1);  in dw_mipi_dsi_clear_err()
1088 	dsi_write(dsi, DSI_INT_MSK0, 0);  in dw_mipi_dsi_clear_err()
1089 	dsi_write(dsi, DSI_INT_MSK1, 0);  in dw_mipi_dsi_clear_err()
1095 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_init()  local
1097 	conn_state->disp_info  = rockchip_get_disp_info(conn_state->type, dsi->id);  in dw_mipi_dsi_connector_init()
1098 	dsi->dphy.phy = conn->phy;  in dw_mipi_dsi_connector_init()
1104 		dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;  in dw_mipi_dsi_connector_init()
1106 	if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {  in dw_mipi_dsi_connector_init()
1108 		conn_state->hold_mode = dsi->disable_hold_mode ? false : true;  in dw_mipi_dsi_connector_init()
1112 	if (dsi->id) {  in dw_mipi_dsi_connector_init()
1121 		dsi->master = dev_get_priv(dev);  in dw_mipi_dsi_connector_init()
1122 		if (!dsi->master)  in dw_mipi_dsi_connector_init()
1129 	if (dsi->dual_channel) {  in dw_mipi_dsi_connector_init()
1145 		dsi->slave = dev_get_priv(dev);  in dw_mipi_dsi_connector_init()
1146 		if (!dsi->slave)  in dw_mipi_dsi_connector_init()
1149 		dsi->lanes /= 2;  in dw_mipi_dsi_connector_init()
1150 		dsi->slave->lanes = dsi->lanes;  in dw_mipi_dsi_connector_init()
1151 		dsi->slave->format = dsi->format;  in dw_mipi_dsi_connector_init()
1152 		dsi->slave->mode_flags = dsi->mode_flags;  in dw_mipi_dsi_connector_init()
1153 		dsi->slave->channel = dsi->channel;  in dw_mipi_dsi_connector_init()
1156 		if (dsi->data_swap)  in dw_mipi_dsi_connector_init()
1174 		dsi->slave->dphy.phy = phy;  in dw_mipi_dsi_connector_init()
1184 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate)  in dw_mipi_dsi_set_hs_clk()  argument
1186 	rate = rockchip_phy_set_pll(dsi->dphy.phy, rate);  in dw_mipi_dsi_set_hs_clk()
1187 	dsi->lane_mbps = rate / 1000 / 1000;  in dw_mipi_dsi_set_hs_clk()
1190 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_host_init()  argument
1192 	dw_mipi_dsi_init(dsi);  in dw_mipi_dsi_host_init()
1193 	dw_mipi_dsi_dpi_config(dsi, &dsi->mode);  in dw_mipi_dsi_host_init()
1194 	dw_mipi_dsi_packet_handler_config(dsi);  in dw_mipi_dsi_host_init()
1195 	dw_mipi_dsi_video_mode_config(dsi);  in dw_mipi_dsi_host_init()
1196 	dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);  in dw_mipi_dsi_host_init()
1197 	dw_mipi_dsi_command_mode_config(dsi);  in dw_mipi_dsi_host_init()
1198 	dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE);  in dw_mipi_dsi_host_init()
1199 	dw_mipi_dsi_line_timer_config(dsi);  in dw_mipi_dsi_host_init()
1200 	dw_mipi_dsi_vertical_timing_config(dsi);  in dw_mipi_dsi_host_init()
1201 	dw_mipi_dsi_dphy_timing_config(dsi);  in dw_mipi_dsi_host_init()
1202 	dw_mipi_dsi_dphy_interface_config(dsi);  in dw_mipi_dsi_host_init()
1203 	dw_mipi_dsi_clear_err(dsi);  in dw_mipi_dsi_host_init()
1206 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id)  in dw_mipi_dsi_vop_routing()  argument
1208 	grf_field_write(dsi, VOPSEL, vop_id);  in dw_mipi_dsi_vop_routing()
1210 	if (dsi->slave)  in dw_mipi_dsi_vop_routing()
1211 		grf_field_write(dsi->slave, VOPSEL, vop_id);  in dw_mipi_dsi_vop_routing()
1214 static void mipi_dphy_init(struct dw_mipi_dsi *dsi)  in mipi_dphy_init()  argument
1218 	mipi_dphy_enableclk_deassert(dsi);  in mipi_dphy_init()
1219 	mipi_dphy_shutdownz_assert(dsi);  in mipi_dphy_init()
1220 	mipi_dphy_rstz_assert(dsi);  in mipi_dphy_init()
1221 	testif_testclr_assert(dsi);  in mipi_dphy_init()
1224 	grf_field_write(dsi, MASTERSLAVEZ, 1);  in mipi_dphy_init()
1227 	grf_field_write(dsi, BASEDIR, 0);  in mipi_dphy_init()
1230 	grf_field_write(dsi, TURNREQUEST, 0);  in mipi_dphy_init()
1231 	grf_field_write(dsi, TURNDISABLE, 0);  in mipi_dphy_init()
1232 	grf_field_write(dsi, FORCETXSTOPMODE, 0);  in mipi_dphy_init()
1233 	grf_field_write(dsi, FORCERXMODE, 0);  in mipi_dphy_init()
1236 	testif_testclr_deassert(dsi);  in mipi_dphy_init()
1238 	if (!dsi->dphy.phy)  in mipi_dphy_init()
1239 		dw_mipi_dsi_phy_init(dsi);  in mipi_dphy_init()
1242 	grf_field_write(dsi, ENABLE_N, map[dsi->lanes]);  in mipi_dphy_init()
1245 	grf_field_write(dsi, ENABLECLK, 1);  in mipi_dphy_init()
1247 	mipi_dphy_enableclk_assert(dsi);  in mipi_dphy_init()
1250 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi)  in dw_mipi_dsi_pre_enable()  argument
1252 	if (dsi->prepared)  in dw_mipi_dsi_pre_enable()
1255 	if (dsi->master)  in dw_mipi_dsi_pre_enable()
1256 		dw_mipi_dsi_pre_enable(dsi->master);  in dw_mipi_dsi_pre_enable()
1258 	dw_mipi_dsi_host_init(dsi);  in dw_mipi_dsi_pre_enable()
1259 	mipi_dphy_init(dsi);  in dw_mipi_dsi_pre_enable()
1260 	mipi_dphy_power_on(dsi);  in dw_mipi_dsi_pre_enable()
1261 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_pre_enable()
1263 	dsi->prepared = true;  in dw_mipi_dsi_pre_enable()
1265 	if (dsi->slave)  in dw_mipi_dsi_pre_enable()
1266 		dw_mipi_dsi_pre_enable(dsi->slave);  in dw_mipi_dsi_pre_enable()
1274 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_prepare()  local
1277 	memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode));  in dw_mipi_dsi_connector_prepare()
1278 	if (dsi->slave) {  in dw_mipi_dsi_connector_prepare()
1279 		dsi->mode.hdisplay /= 2;  in dw_mipi_dsi_connector_prepare()
1280 		memcpy(&dsi->slave->mode, &dsi->mode,  in dw_mipi_dsi_connector_prepare()
1284 	lane_rate = dw_mipi_dsi_get_lane_rate(dsi);  in dw_mipi_dsi_connector_prepare()
1285 	if (dsi->dphy.phy)  in dw_mipi_dsi_connector_prepare()
1286 		dw_mipi_dsi_set_hs_clk(dsi, lane_rate);  in dw_mipi_dsi_connector_prepare()
1288 		dw_mipi_dsi_set_pll(dsi, lane_rate);  in dw_mipi_dsi_connector_prepare()
1290 	if (dsi->slave && dsi->slave->dphy.phy)  in dw_mipi_dsi_connector_prepare()
1291 		dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate);  in dw_mipi_dsi_connector_prepare()
1294 	       dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);  in dw_mipi_dsi_connector_prepare()
1296 	dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id);  in dw_mipi_dsi_connector_prepare()
1297 	dw_mipi_dsi_pre_enable(dsi);  in dw_mipi_dsi_connector_prepare()
1305 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_unprepare()  local
1307 	dw_mipi_dsi_post_disable(dsi);  in dw_mipi_dsi_connector_unprepare()
1313 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_enable()  local
1315 	dw_mipi_dsi_enable(dsi);  in dw_mipi_dsi_connector_enable()
1323 	struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev);  in dw_mipi_dsi_connector_disable()  local
1325 	dw_mipi_dsi_disable(dsi);  in dw_mipi_dsi_connector_disable()
1340 	struct dw_mipi_dsi *dsi = dev_get_priv(dev);  in dw_mipi_dsi_probe()  local
1345 	dsi->base = dev_read_addr_ptr(dev);  in dw_mipi_dsi_probe()
1346 	dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);  in dw_mipi_dsi_probe()
1347 	if (IS_ERR(dsi->grf))  in dw_mipi_dsi_probe()
1348 		return PTR_ERR(dsi->grf);  in dw_mipi_dsi_probe()
1354 	dsi->dev = dev;  in dw_mipi_dsi_probe()
1355 	dsi->pdata = pdata;  in dw_mipi_dsi_probe()
1356 	dsi->id = id;  in dw_mipi_dsi_probe()
1357 	dsi->dual_channel = dev_read_bool(dsi->dev, "rockchip,dual-channel");  in dw_mipi_dsi_probe()
1358 	dsi->data_swap = dev_read_bool(dsi->dev, "rockchip,data-swap");  in dw_mipi_dsi_probe()
1359 	dsi->disable_hold_mode = dev_read_bool(dsi->dev, "disable-hold-mode");  in dw_mipi_dsi_probe()
1361 	rockchip_connector_bind(&dsi->connector, dev, dsi->id, &dw_mipi_dsi_connector_funcs, NULL,  in dw_mipi_dsi_probe()
1660 	struct dw_mipi_dsi *dsi = dev_get_priv(host->dev);  in dw_mipi_dsi_host_transfer()  local
1662 	return dw_mipi_dsi_transfer(dsi, msg);  in dw_mipi_dsi_host_transfer()
1668 	struct dw_mipi_dsi *dsi = dev_get_priv(host->dev);  in dw_mipi_dsi_host_attach()  local
1673 	dsi->lanes = device->lanes;  in dw_mipi_dsi_host_attach()
1674 	dsi->channel = device->channel;  in dw_mipi_dsi_host_attach()
1675 	dsi->format = device->format;  in dw_mipi_dsi_host_attach()
1676 	dsi->mode_flags = device->mode_flags;  in dw_mipi_dsi_host_attach()