90 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)  in musb_h_tx_flush_fifo()  argument
92 	struct musb	*musb = ep->musb;  in musb_h_tx_flush_fifo()
93 	void __iomem	*epio = ep->regs;  in musb_h_tx_flush_fifo()
108 				ep->epnum, csr))  in musb_h_tx_flush_fifo()
114 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)  in musb_h_ep0_flush_fifo()  argument
116 	void __iomem	*epio = ep->regs;  in musb_h_ep0_flush_fifo()
131 			ep->epnum, csr);  in musb_h_ep0_flush_fifo()
141 static inline void musb_h_tx_start(struct musb_hw_ep *ep)  in musb_h_tx_start()  argument
146 	if (ep->epnum) {  in musb_h_tx_start()
147 		txcsr = musb_readw(ep->regs, MUSB_TXCSR);  in musb_h_tx_start()
149 		musb_writew(ep->regs, MUSB_TXCSR, txcsr);  in musb_h_tx_start()
152 		musb_writew(ep->regs, MUSB_CSR0, txcsr);  in musb_h_tx_start()
157 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)  in musb_h_tx_dma_start()  argument
162 	txcsr = musb_readw(ep->regs, MUSB_TXCSR);  in musb_h_tx_dma_start()
166 	musb_writew(ep->regs, MUSB_TXCSR, txcsr);  in musb_h_tx_dma_start()
169 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)  in musb_ep_set_qh()  argument
171 	if (is_in != 0 || ep->is_shared_fifo)  in musb_ep_set_qh()
172 		ep->in_qh  = qh;  in musb_ep_set_qh()
173 	if (is_in == 0 || ep->is_shared_fifo)  in musb_ep_set_qh()
174 		ep->out_qh = qh;  in musb_ep_set_qh()
177 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)  in musb_ep_get_qh()  argument
179 	return is_in ? ep->in_qh : ep->out_qh;  in musb_ep_get_qh()
344 	struct musb_hw_ep	*ep = qh->hw_ep;  in musb_advance_schedule()  local
376 			ep->rx_reinit = 1;  in musb_advance_schedule()
377 			if (ep->rx_channel) {  in musb_advance_schedule()
378 				dma->channel_release(ep->rx_channel);  in musb_advance_schedule()
379 				ep->rx_channel = NULL;  in musb_advance_schedule()
382 			ep->tx_reinit = 1;  in musb_advance_schedule()
383 			if (ep->tx_channel) {  in musb_advance_schedule()
384 				dma->channel_release(ep->tx_channel);  in musb_advance_schedule()
385 				ep->tx_channel = NULL;  in musb_advance_schedule()
390 		musb_ep_set_qh(ep, is_in, NULL);  in musb_advance_schedule()
555 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)  in musb_rx_reinit()  argument
565 	if (ep->is_shared_fifo) {  in musb_rx_reinit()
566 		csr = musb_readw(ep->regs, MUSB_TXCSR);  in musb_rx_reinit()
568 			musb_h_tx_flush_fifo(ep);  in musb_rx_reinit()
569 			csr = musb_readw(ep->regs, MUSB_TXCSR);  in musb_rx_reinit()
570 			musb_writew(ep->regs, MUSB_TXCSR,  in musb_rx_reinit()
579 			musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);  in musb_rx_reinit()
580 		musb_writew(ep->regs, MUSB_TXCSR, 0);  in musb_rx_reinit()
584 		csr = musb_readw(ep->regs, MUSB_RXCSR);  in musb_rx_reinit()
586 			WARNING("rx%d, packet/%d ready?\n", ep->epnum,  in musb_rx_reinit()
587 				musb_readw(ep->regs, MUSB_RXCOUNT));  in musb_rx_reinit()
589 		musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);  in musb_rx_reinit()
594 		musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);  in musb_rx_reinit()
595 		musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);  in musb_rx_reinit()
596 		musb_write_rxhubport(ep->target_regs, qh->h_port_reg);  in musb_rx_reinit()
602 	musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);  in musb_rx_reinit()
603 	musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);  in musb_rx_reinit()
609 		musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);  in musb_rx_reinit()
611 		musb_writew(ep->regs, MUSB_RXMAXP,  in musb_rx_reinit()
614 	ep->rx_reinit = 0;  in musb_rx_reinit()
1387 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)  in musb_bulk_rx_nak_timeout()  argument
1392 	void __iomem		*epio = ep->regs;  in musb_bulk_rx_nak_timeout()
1396 	musb_ep_select(mbase, ep->epnum);  in musb_bulk_rx_nak_timeout()
1397 	dma = is_dma_capable() ? ep->rx_channel : NULL;  in musb_bulk_rx_nak_timeout()
1423 		ep->rx_reinit = 1;  in musb_bulk_rx_nak_timeout()
1921 	struct usb_host_endpoint	*hep = urb->ep;
2124 	struct musb_hw_ep	*ep = qh->hw_ep;  local
2125 	struct musb		*musb = ep->musb;
2126 	void __iomem		*epio = ep->regs;
2127 	unsigned		hw_end = ep->epnum;
2128 	void __iomem		*regs = ep->musb->mregs;
2138 		dma = is_in ? ep->rx_channel : ep->tx_channel;
2140 			status = ep->musb->dma_controller->channel_abort(dma);
2143 				is_in ? 'R' : 'T', ep->epnum,
2150 	if (ep->epnum && is_in) {
2152 		csr = musb_h_flush_rxfifo(ep, 0);
2158 	} else if (ep->epnum) {
2159 		musb_h_tx_flush_fifo(ep);
2173 		musb_h_ep0_flush_fifo(ep);
2176 		musb_advance_schedule(ep->musb, urb, ep, is_in);