101 			dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);  in musb_h_tx_flush_fifo()
229 	dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",  in musb_start_urb()
256 		dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");  in musb_start_urb()
273 			dev_dbg(musb->controller, "SOF for %d\n", epnum);  in musb_start_urb()
283 		dev_dbg(musb->controller, "Start TX%d %s\n", epnum,  in musb_start_urb()
298 	dev_dbg(musb->controller,  in musb_giveback()
421 		dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",  in musb_advance_schedule()
466 	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,  in musb_host_packet_rx()
489 			dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);  in musb_host_packet_rx()
508 			dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);  in musb_host_packet_rx()
696 	dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "  in musb_ep_program()
878 		dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);  in musb_ep_program()
921 			dev_dbg(musb->controller, "start no-DATA\n");  in musb_h_ep0_continue()
924 			dev_dbg(musb->controller, "start IN-DATA\n");  in musb_h_ep0_continue()
929 			dev_dbg(musb->controller, "start OUT-DATA\n");  in musb_h_ep0_continue()
941 			dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",  in musb_h_ep0_continue()
986 	dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",  in musb_h_ep0_irq()
997 		dev_dbg(musb->controller, "STALLING ENDPOINT\n");  in musb_h_ep0_irq()
1001 		dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);  in musb_h_ep0_irq()
1005 		dev_dbg(musb->controller, "control NAK timeout\n");  in musb_h_ep0_irq()
1020 		dev_dbg(musb->controller, "aborting\n");  in musb_h_ep0_irq()
1070 			dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);  in musb_h_ep0_irq()
1124 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);  in musb_host_tx()
1130 	dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,  in musb_host_tx()
1136 		dev_dbg(musb->controller, "TX end %d stall\n", epnum);  in musb_host_tx()
1143 		dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);  in musb_host_tx()
1148 		dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);  in musb_host_tx()
1193 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);  in musb_host_tx()
1252 			dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "  in musb_host_tx()
1321 		dev_dbg(musb->controller, "not complete, but DMA enabled?\n");  in musb_host_tx()
1462 		dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,  in musb_host_rx()
1470 	dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",  in musb_host_rx()
1477 		dev_dbg(musb->controller, "RX end %d STALL\n", epnum);  in musb_host_rx()
1483 		dev_dbg(musb->controller, "end %d RX proto error\n", epnum);  in musb_host_rx()
1491 			dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);  in musb_host_rx()
1514 			dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);  in musb_host_rx()
1519 		dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",  in musb_host_rx()
1565 		dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,  in musb_host_rx()
1615 		dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,  in musb_host_rx()
1648 			dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",  in musb_host_rx()
1672 					dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\  in musb_host_rx()
1764 			dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");  in musb_host_rx()
1885 	dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);  in musb_schedule()
2141 			dev_dbg(musb->controller,
2195 	dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,