494 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in ep0_rxstate()
550 		musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;  in ep0_txstate()
615 		musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;  in musb_read_setup()
617 		musb->ep0_state = MUSB_EP0_STAGE_TX;  in musb_read_setup()
624 		musb->ep0_state = MUSB_EP0_STAGE_RX;  in musb_read_setup()
661 			decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
676 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
685 		switch (musb->ep0_state) {  in musb_g_ep0_irq()
687 			musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;  in musb_g_ep0_irq()
690 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in musb_g_ep0_irq()
694 			    decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
704 	switch (musb->ep0_state) {  in musb_g_ep0_irq()
765 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
776 		musb->ep0_state = MUSB_EP0_STAGE_SETUP;  in musb_g_ep0_irq()
805 			switch (musb->ep0_state) {  in musb_g_ep0_irq()
826 					musb->ep0_state =  in musb_g_ep0_irq()
839 					musb->ep0_state =  in musb_g_ep0_irq()
851 				decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
868 				musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
888 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
939 	switch (musb->ep0_state) {  in musb_g_ep0_queue()
947 				musb->ep0_state);  in musb_g_ep0_queue()
962 	if (musb->ep0_state == MUSB_EP0_STAGE_TX)  in musb_g_ep0_queue()
966 	else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {  in musb_g_ep0_queue()
970 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in musb_g_ep0_queue()
1025 	switch (musb->ep0_state) {  in musb_g_ep0_halt()
1044 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_halt()
1048 		dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);  in musb_g_ep0_halt()