Lines Matching refs:MUSB_CSR0
513 musb_writew(regs, MUSB_CSR0, csr); in ep0_rxstate()
533 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0)); in ep0_txstate()
557 musb_writew(regs, MUSB_CSR0, csr); in ep0_txstate()
618 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY); in musb_read_setup()
619 while ((musb_readw(regs, MUSB_CSR0) in musb_read_setup()
655 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
673 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
677 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
682 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND); in musb_g_ep0_irq()
696 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
870 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
887 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL); in musb_g_ep0_irq()
971 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_queue()
982 musb_writew(regs, MUSB_CSR0, musb->ackpend); in musb_g_ep0_queue()
1033 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_halt()
1043 musb_writew(regs, MUSB_CSR0, csr); in musb_g_ep0_halt()