Lines Matching refs:xceiv
343 switch (musb->xceiv->state) { in musb_otg_timer_func()
347 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_otg_timer_func()
353 otg_state_string(musb->xceiv->state)); in musb_otg_timer_func()
355 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; in musb_otg_timer_func()
359 otg_state_string(musb->xceiv->state)); in musb_otg_timer_func()
374 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
376 switch (musb->xceiv->state) { in musb_hnp_stop()
380 otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
385 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_hnp_stop()
394 otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
422 struct usb_otg *otg = musb->xceiv->otg; in musb_stage0_irq()
436 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
441 switch (musb->xceiv->state) { in musb_stage0_irq()
464 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
469 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
476 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
479 switch (musb->xceiv->state) { in musb_stage0_irq()
482 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
505 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
521 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
532 musb->xceiv->state = OTG_STATE_A_IDLE; in musb_stage0_irq()
558 switch (musb->xceiv->state) { in musb_stage0_irq()
586 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
611 otg_state_string(musb->xceiv->state), devctl, power); in musb_stage0_irq()
614 switch (musb->xceiv->state) { in musb_stage0_irq()
639 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; in musb_stage0_irq()
652 musb->xceiv->state = OTG_STATE_A_SUSPEND; in musb_stage0_irq()
696 switch (musb->xceiv->state) { in musb_stage0_irq()
708 musb->xceiv->state = OTG_STATE_B_HOST; in musb_stage0_irq()
716 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
730 otg_state_string(musb->xceiv->state), devctl); in musb_stage0_irq()
737 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
741 switch (musb->xceiv->state) { in musb_stage0_irq()
758 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
774 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
800 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
801 switch (musb->xceiv->state) { in musb_stage0_irq()
813 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
825 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
826 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
830 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
837 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
1697 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); in musb_mode_show()
1742 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) in musb_vbus_store()
1814 if (musb->xceiv->state != old_state) { in musb_irq_work()
1815 old_state = musb->xceiv->state; in musb_irq_work()
1974 if (!musb->xceiv->io_ops) { in musb_init_controller()
1975 musb->xceiv->io_dev = musb->controller; in musb_init_controller()
1976 musb->xceiv->io_priv = musb->mregs; in musb_init_controller()
1977 musb->xceiv->io_ops = &musb_ulpi_access; in musb_init_controller()
2035 otg_set_host(musb->xceiv->otg, &hcd->self); in musb_init_controller()
2039 musb->xceiv->otg->host = &hcd->self; in musb_init_controller()
2060 musb->xceiv->otg->default_a = 1; in musb_init_controller()
2061 musb->xceiv->state = OTG_STATE_A_IDLE; in musb_init_controller()
2077 musb->xceiv->otg->default_a = 0; in musb_init_controller()
2078 musb->xceiv->state = OTG_STATE_B_IDLE; in musb_init_controller()