236 		prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);  in xhci_link_segments()
335 					cpu_to_le32(LINK_TOGGLE);  in xhci_ring_alloc()
563 		entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);  in xhci_mem_init()
744 	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));  in xhci_setup_addressable_virt_dev()
773 		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);  in xhci_setup_addressable_virt_dev()
776 		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);  in xhci_setup_addressable_virt_dev()
779 		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);  in xhci_setup_addressable_virt_dev()
782 		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);  in xhci_setup_addressable_virt_dev()
806 				slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);  in xhci_setup_addressable_virt_dev()
807 			slot_ctx->tt_info |= cpu_to_le32(TT_PORT(port_num));  in xhci_setup_addressable_virt_dev()
808 			slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));  in xhci_setup_addressable_virt_dev()
817 			cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<  in xhci_setup_addressable_virt_dev()
822 	ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);  in xhci_setup_addressable_virt_dev()
827 		ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<  in xhci_setup_addressable_virt_dev()
834 		ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<  in xhci_setup_addressable_virt_dev()
839 		ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<  in xhci_setup_addressable_virt_dev()
850 			cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |  in xhci_setup_addressable_virt_dev()
860 	ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(8));  in xhci_setup_addressable_virt_dev()