Lines Matching +full:- +full:p
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
17 * USBSS-DEV register interface.
22 * struct cdns3_usb_regs - device controller registers.
52 * @buf_addr: Address for On-chip Buffer operations.
53 * @buf_data: Data for On-chip Buffer operations.
54 * @buf_ctrl: On-chip Buffer Access Control.
122 /* USB_CONF - bitmasks */
131 /* Little Endian access - default */
145 /* DMA clock turn-off enable. */
147 /* DMA clock turn-off disable. */
189 /* USB_STS - bitmasks */
192 * 1 - device is in the configured state.
193 * 0 - device is not configured.
196 #define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK) argument
198 * On-chip memory overflow.
199 * 0 - On-chip memory status OK.
200 * 1 - On-chip memory overflow.
203 #define USB_STS_OV(p) ((p) & USB_STS_OV_MASK) argument
206 * 0 - USB in SuperSpeed mode disconnected.
207 * 1 - USB in SuperSpeed mode connected.
210 #define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK) argument
213 * 0 - single request.
214 * 1 - multiple TRB chain
218 #define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK) argument
221 * 0 - Undefined (value after reset).
222 * 1 - Low speed
223 * 2 - Full speed
224 * 3 - High speed
225 * 4 - Super speed
228 #define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4) argument
233 #define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4)) argument
234 #define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS) argument
235 #define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS) argument
236 #define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS) argument
237 #define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS) argument
240 * 0 - Little Endian order (default after hardware reset).
241 * 1 - Big Endian order
244 #define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK) argument
246 * HS/FS clock turn-off status.
247 * 0 - hsfs clock is always on.
248 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
252 #define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK) argument
254 * PCLK clock turn-off status.
255 * 0 - pclk clock is always on.
256 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
260 #define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK) argument
263 * 0 - Internal reset is active.
264 * 1 - Internal reset is not active and controller is fully operational.
267 #define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK) argument
270 * 0 - disabled
271 * 1 - enabled
277 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
278 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
281 #define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK) argument
284 * 0 - USB device is default state.
285 * 1 - USB device is at least in address state.
288 #define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK) argument
291 * 0 - Entering to L1 LPM state disabled.
292 * 1 - Entering to L1 LPM state enabled.
295 #define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK) argument
298 * 0 - internal VBUS is not detected.
299 * 1 - internal VBUS is detected.
302 #define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK) argument
305 * 0 - L0 State
306 * 1 - L1 State
307 * 2 - L2 State
308 * 3 - L3 State
311 #define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18)) argument
312 #define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18)) argument
313 #define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18)) argument
314 #define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18)) argument
317 * 0 - the disconnect bit for HS/FS mode is set .
318 * 1 - the disconnect bit for HS/FS mode is not set.
321 #define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK) argument
324 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
325 * 1 - High Speed operations in USB2.0 (FS/HS).
328 #define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK) argument
331 * 0 - Entering to U1 state disabled.
332 * 1 - Entering to U1 state enabled.
335 #define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK) argument
338 * 0 - Entering to U2 state disabled.
339 * 1 - Entering to U2 state enabled.
342 #define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK) argument
344 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
348 #define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
349 #define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
350 #define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
351 #define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
352 #define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
353 #define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
354 #define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
355 #define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
356 #define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
357 #define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
358 #define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
359 #define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
361 * DMA clock turn-off status.
362 * 0 - DMA clock is always on (default after hardware reset).
363 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
366 #define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK) argument
369 * 0 - Little Endian order (default after hardware reset).
370 * 1 - Big Endian order.
373 #define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK) argument
375 /* USB_CMD - bitmasks */
386 #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK) argument
393 #define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK) argument
401 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
403 #define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK) argument
405 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
409 #define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK) argument
411 /* USB_ITPN - bitmasks */
418 #define USB_ITPN(p) ((p) & USB_ITPN_MASK) argument
420 /* USB_LPM - bitmasks */
423 #define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK) argument
427 /* USB_IEN - bitmasks */
480 /* USB_ISTS - bitmasks */
528 /* USB_SEL - bitmasks */
531 #define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK) argument
532 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
535 #define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
536 #define select_ep_out (EP_SEL_EPNO(p))
538 /* EP_TRADDR - bitmasks */
540 #define EP_TRADDR_TRADDR(p) ((p)) argument
542 /* EP_CFG - bitmasks */
547 * 1 - isochronous
548 * 2 - bulk
549 * 3 - interrupt
552 #define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK) argument
563 #define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK) argument
566 #define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK) argument
569 #define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK) argument
572 #define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK) argument
574 /* EP_CMD - bitmasks */
600 #define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK) argument
601 #define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9) argument
605 #define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK) argument
607 /* EP_STS - bitmasks */
611 #define EP_STS_STALL(p) ((p) & BIT(1)) argument
629 #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10)) argument
631 #define EP_STS_CCS(p) ((p) & BIT(11)) argument
641 #define EP_STS_HOSTPP(p) ((p) & BIT(16)) argument
644 #define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
645 #define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
646 #define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
647 #define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
652 #define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24) argument
655 #define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK) argument
659 /* EP_STS_SID - bitmasks */
662 #define EP_STS_SID(p) ((p) & EP_STS_SID_MASK) argument
664 /* EP_STS_EN - bitmasks */
690 /* DRBL- bitmasks */
695 /* EP_IEN - bitmasks */
700 /* EP_ISTS - bitmasks */
705 /* USB_PWR- bitmasks */
711 * Enables turning-off Reference Clock.
726 /* USB_CONF2- bitmasks */
740 /* USB_CAP1- bitmasks */
744 * 0x0 - OCP
745 * 0x1 - AHB,
746 * 0x2 - PLB
747 * 0x3 - AXI
748 * 0x4-0xF - reserved
751 #define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0) argument
752 #define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1) argument
753 #define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2) argument
754 #define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3) argument
758 * 0x0 - 8 bit interface,
759 * 0x1 - 16 bit interface,
760 * 0x2 - 32 bit interface
761 * 0x3 - 64 bit interface
762 * 0x4-0xF - reserved
765 #define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4)) argument
766 #define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4)) argument
767 #define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4)) argument
768 #define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4)) argument
772 * 0x0 - OCP
773 * 0x1 - AHB,
774 * 0x2 - PLB
775 * 0x3 - AXI
776 * 0x4-0xF - reserved
779 #define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8)) argument
780 #define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8)) argument
781 #define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8)) argument
782 #define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8)) argument
786 * 0x0 - reserved,
787 * 0x1 - reserved,
788 * 0x2 - 32 bit interface
789 * 0x3 - 64 bit interface
790 * 0x4-0xF - reserved
793 #define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12)) argument
794 #define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12)) argument
798 * 0x0 - USB PIPE,
799 * 0x1 - RMMI,
800 * 0x2-0xF - reserved
803 #define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16)) argument
804 #define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16)) argument
808 * 0x0 - 8 bit PIPE interface,
809 * 0x1 - 16 bit PIPE interface,
810 * 0x2 - 32 bit PIPE interface,
811 * 0x3 - 64 bit PIPE interface
812 * 0x4-0xF - reserved
817 #define DEV_U3PHY_WIDTH_8(p) \ argument
818 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
819 #define DEV_U3PHY_WIDTH_16(p) \ argument
820 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
821 #define DEV_U3PHY_WIDTH_32(p) \ argument
822 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
823 #define DEV_U3PHY_WIDTH_64(p) \ argument
824 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
829 * 0x0 - interface NOT implemented,
830 * 0x1 - interface implemented
832 #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24)) argument
836 * 0x0 - UTMI,
837 * 0x1 - ULPI
839 #define DEV_U2PHY_ULPI(p) ((p) & BIT(25)) argument
843 * 0x0 - 8 bit interface,
844 * 0x1 - 16 bit interface,
847 #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26)) argument
850 * 0x0 - pure device mode
851 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
853 #define USB_CAP1_OTG_READY(p) ((p) & BIT(27)) argument
860 #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28)) argument
862 /* USB_CAP2- bitmasks */
864 * The actual size of the connected On-chip RAM memory in kB:
865 * - 0 means 256 kB (max supported mem size)
866 * - value other than 0 reflects the mem size in kB
868 #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0)) argument
871 * These field reflects width of on-chip RAM address bus width,
873 * 0x0-0x7 - reserved,
874 * 0x8 - support for 4kB mem,
875 * 0x9 - support for 8kB mem,
876 * 0xA - support for 16kB mem,
877 * 0xB - support for 32kB mem,
878 * 0xC - support for 64kB mem,
879 * 0xD - support for 128kB mem,
880 * 0xE - support for 256kB mem,
881 * 0xF - reserved
883 #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8)) argument
885 /* USB_CAP3- bitmasks */
888 /* USB_CAP4- bitmasks */
891 /* USB_CAP5- bitmasks */
894 /* USB_CAP6- bitmasks */
895 /* The USBSS-DEV Controller Internal build number. */
896 #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0)) argument
897 /* The USBSS-DEV Controller version number. */
898 #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24)) argument
905 /* DBG_LINK1- bitmasks */
910 #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0)) argument
916 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8)) argument
918 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
922 * 1: USBSS_DEV will not terminate Far-end receiver termination
927 #define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17)) argument
953 /* DMA_AXI_CTRL- bitmasks */
955 #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0)) argument
957 #define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16) argument
964 /*-------------------------------------------------------------------------*/
966 * USBSS-DEV DMA interface.
977 *Only for ISOC endpoints - maximum number of TRBs is calculated as
978 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
988 * struct cdns3_trb - represent Transfer Descriptor block.
1008 #define TRB_TYPE(p) ((p) << 10) argument
1009 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) argument
1017 /* Cycle bit - indicates TRB ownership by driver or hw*/
1028 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1029 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1045 #define TRB_STREAM_ID(p) ((p) << 16) argument
1046 #define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16) argument
1049 #define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16)) argument
1050 #define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16) argument
1053 #define TRB_LEN(p) ((p) & GENMASK(16, 0)) argument
1056 #define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17)) argument
1057 #define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17) argument
1059 /* transfer_len bitmasks - bits 31:24 */
1060 #define TRB_BURST_LEN(p) (((p) << 24) & GENMASK(31, 24)) argument
1061 #define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24) argument
1064 #define TRB_BUFFER(p) ((p) & GENMASK(31, 0)) argument
1066 /*-------------------------------------------------------------------------*/
1087 /*-------------------------------------------------------------------------*/
1093 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1098 * @trb_pool: transfer ring - array of transaction buffers
1103 * @descmis_req: internal transfer object used for getting data from on-chip
1107 * @num: endpoint number (1 - 15)
1169 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1186 * struct cdns3_request - extended device side representation of usb_request
1222 * struct cdns3_device - represent USB device.
1232 * @zlp_buf - zlp buffer
1249 * @onchip_buffers: number of available on-chip buffers.
1250 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1265 /* generic spin-lock for drivers */