Lines Matching refs:ufshcd_readl

87 	while ((ufshcd_readl(hba, reg) & mask) != val) {  in ufshcd_wait_for_register()
89 			if ((ufshcd_readl(hba, reg) & mask) != val)  in ufshcd_wait_for_register()
143 	if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)  in ufshcd_ready_for_uic_cmd()
154 	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &  in ufshcd_get_uic_cmd_result()
163 	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);  in ufshcd_get_dme_attr_val()
172 	return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &  in ufshcd_is_device_present()
209 		intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);  in ufshcd_send_uic_cmd()
430 	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);  in ufshcd_enable_intr()
479 	reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);  in ufshcd_make_hba_operational()
580 	return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)  in ufshcd_is_hba_active()
744 	return ufshcd_readl(hba, REG_UFS_VERSION);  in ufshcd_get_ufs_version()
752 	return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;  in ufshcd_get_upmcrs()
911 		intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);  in ufshcd_send_command()
2016 	hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);  in ufshcd_probe()
2045 	ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),  in ufshcd_probe()