drivers/timer/tsc_timer.c

5  * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7  * SPDX-License-Identifier:	GPL-2.0+
19 #include <asm/u-boot-x86.h>
26  * According to Intel 64 and IA-32 System Programming Guide,
46 	/* TNG - Intel Atom processor Z3400 series */
48 	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
50 	/* ANN - Intel Atom processor Z3500 series */
66 	return -1;  in match_cpu()
69 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
89 	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)  in cpu_mhz_from_msr()
92 	cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);  in cpu_mhz_from_msr()
103 	debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);  in cpu_mhz_from_msr()
128  * non-virtualized hardware.
132  *  - the PIT is running at roughly 1.19MHz
134  *  - each IO is going to take about 1us on real hardware,
137  *    update - anything else implies a unacceptably slow CPU
140  *  - with 256 PIT ticks to read the value, we have 214us to
144  *  - We're doing 2 reads per loop (LSB, MSB), and we expect
149  *  - if the PIT is stuck, and we see *many* more reads, we
179 	*deltap = rdtsc() - prev_tsc;  in pit_expect_msb()
208 	 * Counter 2, mode 0 (one-shot), binary count  in quick_pit_calibrate()
212 	 * final output frequency as a decrement-by-one),  in quick_pit_calibrate()
225 	 * to do that is to just read back the 16-bit counter  in quick_pit_calibrate()
232 			if (!pit_expect_msb(0xff-i, &delta, &d2))  in quick_pit_calibrate()
238 			delta -= tsc;  in quick_pit_calibrate()
249 			if (!pit_verify_msb(0xfe - i))  in quick_pit_calibrate()
267 	 * kHz = ticks / time-in-seconds / 1000;  in quick_pit_calibrate()
268 	 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000  in quick_pit_calibrate()
269 	 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)  in quick_pit_calibrate()
290 	return get_ms_timer() - base;  in get_timer()
310 	while ((int64_t)(stop - get_ticks()) > 0)  in __udelay()
313 		 * Add a 'pause' instruction on qemu target,  in __udelay()
326 	*count = now_tick - gd->arch.tsc_base;  in tsc_timer_get_count()
335 	gd->arch.tsc_base = rdtsc();  in tsc_timer_probe()
341 	if (!uc_priv->clock_rate) {  in tsc_timer_probe()
351 		uc_priv->clock_rate = fast_calibrate * 1000000;  in tsc_timer_probe()
362 	{ .compatible = "x86,tsc-timer", },